AX88796LF ASIX Electronics, AX88796LF Datasheet - Page 40

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AX88796LF

Manufacturer Part Number
AX88796LF
Description
3-in-1 Local CPU Bus Fast Rthernet Controller
Manufacturer
ASIX Electronics
Datasheet

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5.2 The Embedded PHY Registers
The MII management 16-bit register set implemented is as follows. And the following sub-section will describes each
field of the registers. The format for the “FIELD” descriptions is as follows: the first number is the register number, the
second number is the bit position in the register and the name of the instantiated pad is in capital letters. The format for
the “TYPE” descriptions is as follows: R = read, W = write, LH = latch high, NA = not applicable.
Tab - 14 The Embedded PHY Registers
ADDRESS
22 - 24
25 - 27
8 - 15
16
17
18
19
20
21
28
29
30
31
0
1
2
3
4
5
6
7
AX88796 L
MR22 -24 Analog Test Registers
MR25 -27 Analog Test (tuner) Registers
MR8 -15 (Reserved)
NAME
MR16
MR17
MR18
MR19
MR20
MR21
MR28
MR29
MR30
MR31
MR0
MR1
MR2
MR3
MR4
MR5
MR6
MR7
Control
Status
PHY Identifier 1
PHY Identifier 2
Autonegotiation Advertisement
Autonegotiation Link Partner Ability
Autonegotiation Expansion
Next Page Transmit
PCS Control Register
Autonegotiation (read register A)
Autonegotiation (read register B)
Analog Test Register
User-defined Register
RXER Counter
Device Specific 1
Device Specific 2
Device Specific 3
Quick Status Register
3-in-1 Local Bus Fast Ethernet Controller
DESCRIPTION
40
ASIX ELECTRONICS CORPORATION
DEFAULT(Hex Code)
BB10h
01E1h
3000h
7849h
0180h
0000
0000
0000
0000
0000
0000
0000
2080
0000
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-
-
-
-
-
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