AX88796LF ASIX Electronics, AX88796LF Datasheet - Page 37

• Manufacturer Part Number: AX88796LF
• Description: 3-in-1 Local CPU Bus Fast Rthernet Controller
• Manufacturer: ASIX Electronics

5.1.10 Inter-frame gap Segment 1(IFGS1) Offset 12H (Read/Write)
5.1.11 Inter-frame gap Segment 2(IFGS2) Offset 13H (Read/Write)
5.1.12 MII/EEPROM Management Register (MEMR) Offset 14H
(Read/Write)
5.1.13 Test Register (TR) Offset 15H (Write)
FIELD
FIELD
FIELD
FIELD
FIELD
5.1.9 Inter-frame gap (IFG) Offset 16H (Read/Write)
6:0
6:0
6:0
7:5
2:0
7
7
7
7
6
5
4
3
2
1
0
4
3
AX88796 L
EECLK EECLK:
NAME
NAME
NAME
NAME
NAME
TF16T Test for Collision, default value is logic 0 (User always keep the default value unchanged)
MDIR
EECS
MDO
MDC
EEO
MDI
TPE
IFG
IFG
IFG
EEI
IFG
-
-
-
-
Reserved
Inter-frame Gap. Default value 15H.
Reserved
Inter-frame Gap Segment 1. Default value 0cH.
Reserved
Inter-frame Gap Segment 2. Default value 12H.
EEO : (Read only)
EEI
EECS
MDO
MDI: (Read only)
MII STA MDIO signal Direction
let MDIO as output signal.
MDC
Reserved
Test pin Enable, default value is logic 0 (User always keep the default value unchanged)
Select Test Pins Output, default value is logic 0 (User always keep the default value
unchanged)
MII Read Control Bit, asserts this bit let MDIO signal as the input signal. Deassert this bit
EEPROM Clock
EEPROM Data Out value. That reflects Pin-48 EEDO value.
EEPROM Data In. That output to Pin-49 EEDI as EEPROM data input value.
EEPROM Chip Select
MII Data Out. The value reflects to Pin-66 MDIO when MDIR=0.
MII Data In. That reflects Pin-66 MDIO value.
MII Clock. This value reflects to Pin-67 MDC.
3-in-1 Local Bus Fast Ethernet Controller
37
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
ASIX ELECTRONICS CORPORATION