PXA250 INTEL [Intel Corporation], PXA250 Datasheet - Page 37

• Manufacturer Part Number: PXA250
• Description: Intel-R PXA250 and PXA210 Applications Processors
• Manufacturer: INTEL [Intel Corporation]

4.6.3
4.6.4
Datasheet
Figure 5. Hardware Reset Timing
Table 14. Hardware Reset Timing Specifications
Figure 6. GPIO Reset Timing
Watchdog Reset Timing
Watchdog Reset is an internally generated reset and therefore has no external pin dependencies.
The nRESETOUT pin is the only indicator of Watchdog Reset, and it stays asserted for t
Refer to Figure 5, “Hardware Reset Timing” on page 37.
GPIO Reset Timing
GPIO Reset is generated externally, and the source is reconfigured as a standard GPIO as soon as
the reset propagates internally. The clocks module is not reset by GPIO Reset, so the timing varies
based on the frequency of clock selected and if the Clocks and Power Manager is in the Frequency
Change Sequence when GPIO Reset is asserted (see Section 4.5.1, “32.768 kHz Oscillator
Specifications” on page 33.) Figure 6, “GPIO Reset Timing” on page 37 shows the possible timing
of GPIO Reset.
tDHW_NRESET
tDHW_OUT_A
tDHW_OUT
Symbol
nRESET_OUT
nRESET_OUT
Electrical, Mechanical, and Thermal Specification — PXA250 and PXA210
nRESET
GP[1]
Note: nBATT_FAULT and nVDD_FAULT must be high before nRESET is
deasserted or the application processor will enter Sleep Mode
Minimum assertion time of nRESET
Delay between nRESET Asserted and
nRESET_OUT Asserted
Delay between nRESET deasserted and
nRESET_OUT deasserted
Note: nBATT_FAULT and nVDD_FAULT must be high before nRESET is
Note: nBA TT_FAULT and nVDD_F AULT must be high before nRESET is deasserted
deasserted or the PXA250 applications processor enters Sleep Mode.
or the Cotulla will enter Sleep Mode
Description
t
DHW_OUT_A
t
A_GP[1]
t
DHW_OUT_A
0.001
18.1
Min
0
t
t
DHW_OUT
DHW_NRESET
Typical
t
DHW_OUT
0.001
Max
18.2
DHW_OUT
Units
ms
ms
ms
37
.