HT68F14 HOLTEK [Holtek Semiconductor Inc], HT68F14 Datasheet - Page 102

• Manufacturer Part Number: HT68F14
• Description: Enhanced I/O Flash Type MCU
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

HT68F13/HT68F14/HT68F15
Enhanced I/O Flash Type MCU
Note:
Rev. 1.10
Flag TnAF
Flag TnBF
Flag TnPF
CCRA Int.
CCRB Int.
CCRP Int.
(TnBOC=1)
(TnBOC=0)
TPnB Pin
TPnB Pin
TnBPOL
TnPAU
Counter Value
CCRA
CCRB
TnON
1. Here TnCCLR=1 therefore CCRA clears the counter and determines the PWM period
2. TnPWM [1:0] =11 therefore the PWM is centre aligned
3. The internal PWM function continues running even when TnBIO [1:0] = 00 or 01
4. CCRA controls the TPnB PWM period and CCRB controls the TPnB PWM duty
5. CCRP will generate an interrupt request when the counter decrements to its zero value
Single Pulse Output Mode
To select this mode, the required bit pairs, TnAM1, TnAM0 and TnBM1, TnBM0 should be set to 10
respectively and also the corresponding TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits should be set to
11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse
on the TM output pin.
The trigger for the pulse TPnA output leading edge is a low to high transition of the TnON bit, which
can be implemented using the application program. The trigger for the pulse TPnB output leading edge
is a compare match from Comparator B, which can be implemented using the application program.
However in the Single Pulse Mode, the TnON bit can also be made to automatically change from low
to high using the external TCKn pin, which will in turn initiate the Single Pulse output of TPnA. When
the TnON bit transitions to a high level, the counter will start running and the pulse leading edge of
TPnA will be generated. The TnON bit should remain high when the pulse is in its active state. The
generated pulse trailing edge of TPnA and TPnB will be generated when the TnON bit is cleared to
zero, which can be implemented using the application program or when a compare match occurs from
Comparator A.
Duty Cycle set by CCRB
PWM Period set by CCRA
ETM PWM Mode -- Centre Aligned
102
Pause
TnCCLR = 1; TnBM [1:0] = 10;
TnPWM [1:0] = 11
Resume
Output controlled
by other pin-shared
function
Stop
Output Pin
Reset to Initial value
Counter
Restart
February 9, 2011
Output Inverts
when TnBPOL is high
Time