DM9000A_06 DAVICOM [Davicom Semiconductor, Inc.], DM9000A_06 Datasheet - Page 23

• Manufacturer Part Number: DM9000A_06
• Description: Ethernet Controller with General Processor Interface
• Manufacturer: DAVICOM [Davicom Semiconductor, Inc.]

6.26 Operation Test Control Register ( 2EH )
6.27 Special Mode Control Register ( 2FH )
Final
Version: DM9000A-17-DS-F01
May 10, 2006
3~0
7~6
2~0
6~3
Bit
Bit
5
4
5
4
3
7
2
1
0
RESERVED
RESERVED
ONEPM
PHYOP
SM_EN
Name
Name
IFGS
SCC
SOE
DTU
SCS
FLC
FB1
FB0
Default
Default
P0,RW
P0,RW
P0,RW
P0,RW
P0,RW
P0,RW
P0,RW
P0,RW
P0,RW
P0,RW
P0,RW
P0,RW
P0,RW
Internal SRAM Chip-Select Always ON
Disable TX Underrun Retry
Disable to re-transmit the underruned packet
One Packet Mode
When set, only one packet transmit command can be issued before transmit
completed.
When cleared, at most two packet transmit command can be issued before
transmit completed.
Inter-Frame Gap Setting
0XXX: 96-bit
1000: 64-bit
1001: 72-bit
1010:80-bit
1011:88-bit
1100:96-bit
1101:104-bit
1110: 112-bit
1111:120-bit
System Clock Control
Set the internal system clock.
00: 50Mhz
01: 20MHz
10: 100MHz
11: Reserved
Reserved
Internal SRAM Output-Enable Always ON
Internal PHY operation mode for testing
Special Mode Enable
Reserved
Force Late Collision
Force Longest Back-off time
Force Shortest Back-off time
Ethernet Controller with General Processor Interface
Description
Description
DM9000A
23