DM9008AEP_06 DAVICOM [Davicom Semiconductor, Inc.], DM9008AEP_06 Datasheet
DM9008AEP_06
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DM9008AEP_06 Summary of contents
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DAVICOM Semiconductor, Inc. with General Processor Interface Preliminary Version: DM9008A-DS-P02 Apr. 11, 2006 Ethernet Controller with General Processor Interface DM9008AEP Ethernet Controller DATA SHEET DM9008AEP Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 1 ...
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General Description........................................................................................................... 6 2. Block Diagram.................................................................................................................... 6 3. Features.............................................................................................................................. 7 4. Pin Configuration............................................................................................................... 8 5. Pin Description .................................................................................................................. 9 5.1 Processor Interface................................................................................................................................... 9 5.2 EEPROM Interface ................................................................................................................................... 9 5.3 Clock Interface ........................................................................................................................................ 10 5.4 LED Interface .......................................................................................................................................... 10 5.5 ...
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General purpose control Register ( 1EH ) (in 8-bit mode) ................................................................. 18 6.19 General purpose Register ( 1FH ) ........................................................................................................ 19 6.20 TX SRAM Read Pointer Address Register (22H~23H) ........................................................................ 19 6.21 RX SRAM Write Pointer Address Register (24H~25H) ...
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Auto-negotiation Advertisement Register (ANAR .......................................................................... 31 8.6 Auto-negotiation Link Partner Ability Register (ANLPAR) – 05 .............................................................. 32 8.7 Auto-negotiation Expansion Register (ANER)- 06.................................................................................. 33 8.8 DAVICOM Specified Configuration Register (DSCR) – 16..................................................................... 33 Reserved .............................................................................................................................. 34 Force ...
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Power Decoupling Capacitors .............................................................................................................. 46 11.41 DM9008A + DM8606A Circuit ............................................................................................................ 47 11.5 Magnetics Selection Guide ................................................................................................................... 48 11.6 Crystal Selection Guide ........................................................................................................................ 48 12. Package Information ..................................................................................................... 49 13. Ordering Information..................................................................................................... 50 Preliminary Version: DM9008A-DS-P02 Apr. 11, 2006 ...
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General Description The DM9008A is a fully integrated and cost-effective low pin count Ethernet controller with a general processor interface, a Medial Access Control (MAC), a 10Base-T PHY and 16K Byte SRAM designed with low power and ...
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Features ■ 48-pin LQFP ■ Supports processor interface: byte/word of I/O command to internal memory data operation ■ Comply to 10BASE-T of IEEE 802.3 with HP Auto-MDIX ■ Supports back pressure mode for half-duplex mode flow control ■ Support ...
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Pin Configuration CS# LED2 LED1 PWRST# TEST VDD X2 X1 GND SD RXGND BGGND Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 Ethernet Controller with General Processor Interface DM9008A ...
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Pin Description I = Input O = Output # = asserted low 5.1 Processor Interface Pin No. Pin Name 35 IOR# 36 IOW# 37 CS# 32 CMD 34 INT O,PD 18,17,16,1 4,13,12,11 SD0~7 I/O,PD ,10 31, SD8_GP1, 29, SD9_GP2, ...
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Clock Interface Pin No. Pin Name 5.4 LED Interface Pin No. Pin Name 39 LED1 38 LED2 5.5 10/100 PHY/Fiber Pin No. Pin Name BGGND 1 BGRES 2 RXVDD25 9 TXVDD25 3 ...
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Power Pins Pin No. Pin Name 23,30,42 VDD 15,33,45 GND 5.8 strap pins table 1: pull-high 1K~10K, 0: floating (default) Pin No. Pin Name Polarity of INT 20 EECK 1: INT pin low active; 0: INT pin high active ...
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Vendor Control and Status Register Set The DM9008A implements several control and status registers, which can be accessed by the host. These CSRs Register NCR Network Control Register NSR Network Status Register TCR TX Control Register TSR I TX ...
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MRCMDX Memory Data Pre-Fetch Read Command Without Address Increment Register MRCMDX1 Memory Data Read Command With Address Increment Register MRCMD Memory Data Read Command With Address Increment Register MRRL Memory Data Read_ address Register Low Byte MRRH Memory Data Read_ ...
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Network Status Register (01H) Bit Name Default 7 RESERVED X,RO 6 LINKST X,RO P0, 5 WAKEST RW/C1 4 RESERVED 0,RO PHS0, 3 TX2END RW/C1 PHS0, 2 TX1END RW/C1 1 RXOV PHS0,RO RX FIFO Overflow 0 RESERVED 0,RO 6.3 TX ...
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TX Status Register II ( 04H ) for packet index I I Bit Name Default 7 TJTO PHS0, PHS0, PHS0, PHS0,RO 3 COL PHS0, PHS0,RO 1:0 RESERVED 0,RO 6.6 RX Control ...
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Receive Overflow Counter Register ( 07H ) Bit Name Default 7 RXFU PHS0,R/C 6:0 ROC PHS0,R/C 6.9 Back Pressure Threshold Register (08H) Bit Name Default PHS3, 7:4 BPHW RW PHS7, 3:0 JPT RW 6.10 Flow Control Threshold Register ( ...
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RX/TX Flow Control Register ( 0AH ) Bit Name Default 7 TXP0 HPS0,RW 6 TXPF HPS0,RW 5 TXPEN HPS0,RW 4 BKPA HPS0,RW 3 BKPM HPS0,RW 2 RXPS HPS0,R/C 1 RXPCS HPS0,RO 0 FLCE HPS0,RW 6.12 EEPROM & PHY Control ...
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Wake Up Control Register ( 0FH ) (in 8-bit mode) Bit Name Type 7:6 RESERVED 0,RO 5 LINKEN P0,RW 4 SAMPLEEN P0,RW 3 MAGICEN P0,RW 2 LINKST P0,RO 1 SAMPLEST P0,RO 0 MAGICST P0,RO 6.16 Physical Address Register ( ...
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General purpose Register ( 1FH ) Bit Name Default 7 RESERVED 0,RO 6-4 GPO PH0,RW PH0,RW 3:1 GPIO 0 PHYPD 1,WO 6.20 TX SRAM Read Pointer Address Register (22H~23H) Bit Name Default 7:0 TRPAH PS0,RO 7:0 TRPAL PS0.RO 6.21 ...
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ONEPM PH0,RW 3~0 IFGS PH0,RW 6.26 Operation Test Control Register ( 2EH ) Bit Name Default 7~6 SCC PH0,RW 5 RESERVED PH0,RW 4 SOE PH0,RW 3 SCS PH0,RW 2~0 PHYOP PH0,RW 6.27 Special Mode Control Register ( 2FH ) ...
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Early Transmit Control/Status Register ( 30H ) Bit Name Default 7 ETE HPS0 ETS2 HPS0,RO 5 ETS1 HPS0,RO 4~2 RESERVED 000,RO 1~0 ETT HPS0,RW 6.29 Check Sum Control Register ( 31H ) Bit Name Default 7~3 RESERVED ...
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MII P0,RW 6.32 Processor Bus Control Register ( 38H ) Bit Name Default 7:5 CURR P011,RO 4 Reserved P0,RW 3 GPIO P0,RW 2 Reserved P0,RW 1 IOW_SPIKE P0,RW 0 IOR_SPIKE P1,RW Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 Ethernet Controller ...
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INT Pin Control Register ( 39H ) Bit Name Default 7:2 Reserved PS0,RO 1 INT_TYPE PET0,RW 0 INT_POL PET0,RW 6.34 System Clock Turn ON Control Register ( 50H ) Bit Name Default 7:1 Reserved - 0 DIS_CLK P0,W 6.35 ...
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Memory Data Pre-Fetch Read Command without Address Increment Register (F0H) Bit Name Default 7:0 MRCMDX X,RO 6.37 Memory Data Read Command without Address Increment Register (F1H) Bit Name Default 7:0 MRCMDX1 X,RO 6.38 Memory Data Read Command with Address ...
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Interrupt Status Register (FEH) Bit Name Default 7 IOMODE T0 RESERVED RO 5 LNKCHG PHS0,RW/C1 4 UDRUN PHS0,RW/C1 3 ROO PHS0,RW/ PHS0,RW/ PHS0,RW/ PHS0,RW/C1 6.45 Interrupt Mask Register (FFH) Bit Name ...
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EEPROM Format name Word MAC address 0 Auto Load Control 3 Vendor ID 4 Product ID 5 pin control 6 Wake-up mode control 7 Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 Ethernet Controller with General Processor Interface offset 0~5 6 ...
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MII Register Description ADD Name CONTR Reset Loop Speed Auto-N OL back select Enable STATUS T4 TX FDX TX HDX 10 FDX Cap. Cap. Cap. Cap ...
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Loopback 0.13 Speed selection 0.12 Auto-negotiatio n enable 0.11 Power down 0.10 Isolate 0.9 Restart Auto-negotiation 0.8 Duplex mode 0.7 Collision test Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 Ethernet Controller with General Processor Interface returning a value of one ...
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Reserved 8.2 Basic Mode Status Register (BMSR Bit Bit Name 1.15 100BASE-T4 1.14 100BASE-TX full-duplex 1.13 100BASE-TX half-duplex 1.12 10BASE-T full-duplex 1.11 10BASE-T half-duplex 1.10-1.7 Reserved 1.6 MF preamble suppression 1.5 Auto-negotiation Complete 1.4 Remote fault Auto-negotiation ...
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Link status 1.1 Jabber detect 1.0 Extended capability 8.3 PHY ID Identifier Register #1 (PHYID1 The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM9008A. The Identifier consists of a concatenation ...
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Auto-negotiation Advertisement Register (ANAR This register contains the advertised abilities of this DM9008A device as they will be transmitted to its link partner during Auto-negotiation. Bit Bit Name 4.15 NP 4.14 ACK 4.13 RF 4.12-4.1 Reserved 1 ...
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Auto-negotiation Link Partner Ability Register (ANLPAR) – 05 This register contains the advertised abilities of the link partner when received during Auto-negotiation. Bit Bit Name 5.15 NP 5.14 ACK 5.13 RF 5.12-5.1 Reserved 1 5.10 FCS 5.9 T4 5.8 ...
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Selector 8.7 Auto-negotiation Expansion Register (ANER)- 06 Bit Bit Name 6.15-6.5 Reserved 6.4 PDF 6.3 LP_NP_ABL E 6.2 NP_ABLE 6.1 PAGE_RX 6.0 LP_AN_ABL E 8.8 DAVICOM Specified Configuration Register (DSCR) – 16 Bit Bit Name 16.15 BP_4B5B 16.14 BP_SCR ...
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BP_ADPOK 16.11 Reserved 16.10 TX/FX 16.9 Reserved 16.8 Reserved 16.7 F_LINK_100 16.6 SPLED_CTL 16.5 COLLED_CT L 16.4 RPDCTR-EN 16.3 SMRST 16.2 MFPSC Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 Ethernet Controller with General Processor Interface 0 = Normal operation 0, ...
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SLEEP 16.0 RLOUT 8.9 DAVICOM Specified Configuration and Status Register (DSCSR Bit Bit Name Default 17.15- RESERV 1111, RO Reserved 17.12 ED 17.11- Reserved 0, RO 17.9 17.8- PHYADR (PHYADR), 17.4 [4:0] RW 17.3- ANMB[ ...
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Configuration/Status (10BTCSR Bit Bit Name Default 18.15 Reserved 0, RO 18.14 LP_EN 1, RW 18.13 HBE 1,RW 18.12 SQUELCH 1, RW 18.11 JABEN 1, RW 18.10 Reserved 0, RW 18.9- Reserved 0, RO 18.1 18.0 POLR ...
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FORCE_FEF 20.11-20 Reserved .8 20.7 MDIX_CNTL MDI/MDIX, 20.6 AutoNeg_lpbk 20.5 Mdix_fix Value 20.4 Mdix_down 20.3 MonSel1 20.2 MonSel0 20.1 Reserved 20.0 PD_value Preliminary Version: DM9008AEP-DS-P03 Dec. 14, 2006 Ethernet Controller with General Processor Interface 0: normal SD signal. 0,RW ...
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Functional Description 9.1 Host Interface The host interface is a general processor local bus that using chip select (pin CS#) to access DM9008A. Pin CS# is default low active which can be re-defined by EEPROM setting. There are only ...
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Operation The 10Base-T transceiver is IEEE 802.3 compliant. When the DM9008A is operating in 10Base-T mode, the coding scheme is Manchester. Data processed for transmit is presented to the MII interface in nibble format, converted to a serial ...
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Power Reduced Mode The Signal detect circuit is always turned to monitor whether there is any signal on the media (cable disconnected). The DM9008A automatically turns off the power and enters the Power Reduced mode, whether its operation mode ...
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DC and AC Electrical Characteristics 10.1 Absolute Maximum Ratings ( 25°C ) Symbol D Supply Voltage VDD V DC Input Voltage (VIN Output Voltage(VOUT) OUT Tstg Storage Temperature range TC Case Temperature TA Ambient Temperature LT ...
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AC Electrical Characteristics & Timing Waveforms 10.3.1 Oscillator/Crystal Timing Symbol Parameter T OSC Clock Cycle CKC T OSC Pulse Width High PWH T OSC Pulse Width Low PWL 10.3.2 Processor I/O Read Timing C S#, ...
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Processor I/O Write Timing CS# , CMD IOW# SD IO16 Symbol T CS#,CMD valid to IOW# valid 1 T IOW# Width 2 T System Data(SD) Setup Time 3 T System Data(SD) Hold Time 4 T IOW# Invalid to CS#,CMD ...
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EEPROM Interface Timing EECS EECK EEDIO Symbol T EECK Frequency 1 T2 EECS Setup Time T EECS Hold Time 3 T EEDIO Setup Time when output 4 T5 EEDIO Hold Time when output T EEDIO Setup Time when input ...
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Application Notes 11.1 Network Interface Signal Routing Place the transformer as close as possible to the RJ-45 connector. Place all the 50Ω resistors as close as possible to the DM9008A RXI± and TXO± pins. Traces routed from RXI± and ...
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Non HP Auto-MDIX Transformer Application 11.4 Power Decoupling Capacitors Davicom Semiconductor recommends placing all the decoupling capacitors for all power supply pins as close as possible to the power pads of the DM9008A (The best placed distance is < ...
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DM9008A + DM8606A Circuit SD4 BGGND 13 48 SD3 AGND 14 47 GND SD2 GND 16 45 SD1 SD0 EEDIO VDD 19 42 EEDCK TEST 20 41 EEDCS PWRST# 21 ...
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Magnetics Selection Guide Refer to Table 1 for transformer requirements. Transformers, meeting these requirements, are available from a variety of magnetic manufacturers. Designers should test and qualify all magnetics Manufacturer Pulse Engineering Delta YCL MAGCOM Halo Nano Pulse Inc. ...
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Package Information LQFP 48L (F.P. 2mm) Outline Dimensions Symbol Dimensions in inches Min. Nom. Max 0.063 A1 0.002 - 0.006 A2 0.053 0.055 0.057 b 0.007 0.009 0.011 b1 0.007 0.008 0.009 C 0.004 - 0.008 ...
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Ordering Information Part Number Pin Count DM9008AEP 48 Disclaimer The information appearing in this publication is believed to be accurate. Integrated circuits sold by DAVICOM Semiconductor are covered by the warranty and patent indemnification provisions stipulated in the terms ...