DM9008AEP_06 DAVICOM [Davicom Semiconductor, Inc.], DM9008AEP_06 Datasheet - Page 34
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DM9008AEP_06
Manufacturer Part Number
DM9008AEP_06
Description
Ethernet Controller with General Processor Interface
Manufacturer
DAVICOM [Davicom Semiconductor, Inc.]
Datasheet
1.DM9008AEP_06.pdf
(50 pages)
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Preliminary
Version: DM9008AEP-DS-P03
Dec. 14, 2006
16.12
16.11
16.10
16.9
16.8
16.7
16.6
16.5
16.4
16.3
16.2
COLLED_CT
RPDCTR-EN
F_LINK_100
SPLED_CTL
BP_ADPOK
Reserved
Reserved
Reserved
SMRST
MFPSC
TX/FX
L
0, RW
1, RW
0, RW
0, RW
0, RW
0, RW
1, RW
0, RW
1, RW
0, RO
0, RW
0 = Normal operation
BYPASS ADPOK
Force signal detector (SD) active. This register is for debug
only, not release to customer
1=Forced SD is OK,
0=Normal operation
Reserved
Force to 0 in application.
100BASE-TX/FX Mode Control
1 = 100BASE-TX operation
0 = 100BASE-FX operation
Reserved
Reserved
Force to 0 in application.
Force Good Link in 100Mbps
0 = Normal 100Mbps operation
1 = Force 100Mbps good link status
This bit is useful for diagnostic purposes
Reserved
Force to 0 in application.
Reserved
Force to 0 in application.
Reduced Power Down Control Enable
This bit is used to enable automatic reduced power down
0 = Disable automatic reduced power down
1 = Enable automatic reduced power down
Reset State Machine
When writes 1 to this bit, all state machines of PHY will be
reset. This bit is self-clear after reset is completed
MF Preamble Suppression Control
Frame preamble suppression control bit
1 = MF preamble suppression bit on
0 = MF preamble suppression bit off
Ethernet Controller with General Processor Interface
DM9008AEP
34
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