DM9008AEP_06 DAVICOM [Davicom Semiconductor, Inc.], DM9008AEP_06 Datasheet - Page 27
![no-image](/images/no-image-200.jpg)
DM9008AEP_06
Manufacturer Part Number
DM9008AEP_06
Description
Ethernet Controller with General Processor Interface
Manufacturer
DAVICOM [Davicom Semiconductor, Inc.]
Datasheet
1.DM9008AEP_06.pdf
(50 pages)
ADD
00
01
02
03
04 Auto-Neg.
05
06 Auto-Neg.
16
17
18
8. MII Register Description
Key to Default
In the register description that follows, the default
column takes the form:
<Reset Value>, <Access Type> / <Attribute(s)>
Where:
<Reset Value>:
<Access Type>:
8.1 Basic Mode Control Register (BMCR) - 00
Preliminary
Version: DM9008AEP-DS-P03
Dec. 14, 2006
STATUS
Advertise
Link Part.
Expansio
Specifie
Specifie
Conf/Stat
Conf/Stat
CONTR
PHYID1
PHYID2
Config.
Name
Ability
10T
OL
n
d
d
0.15
Bit
X
1
0
Reset
Page
Page
Rsvd
Cap.
Next
Next
T4
LP
15
0
0
0
1
FLP Rcv
TX FDX
Enable
Bit set to logic one
Bit set to logic zero
No default value
Loop
back
Cap.
Ack
Ack
14
LP
LP
Bit Name
0
1
0
0
Reset
TX HDX
Remote
Speed
Enable
select
Cap.
Fault
HBE
RF
13
LP
1
1
0
1
Reversed
10 FDX
Auto-N
Enable
Enable
SQUE
Cap.
12
1
1
0
1
Reserved
Reserved
0, RW/SC Reset
Default
10 HDX
Power
Down
Enable
Cap.
11
JAB
0
1
0
1
Reserved
Reserved
Reserve
Isolate
Adv
FC
FC
LP
10
0
0
0
d
1=Software reset
0=Normal operation
This bit sets the status and controls the PHY registers to their
default states. This bit, which is self-clearing, will keep
Restart
Auto-N
Adv
LP
9
0
0
T4
T4
Reserved
0000
TX FDX
TX FDX
Duplex
Full
Adv
LP
8
1
1
Ethernet Controller with General Processor Interface
Model No.
TX HDX
TX HDX
01010
Test
<Attribute (s)>:
Coll.
Adv
LP
7
0
1
PHY ADDR [4:0]
RO = Read only
RW = Read/Write
SC = Self clearing
P = Value permanently set
LL = Latching low
LH = Latching high
10 FDX
10 FDX
Pream.
Supr.
Adv
LP
6
1
0
10 HDX
10 HDX
Compl.
Description
Auto-N
Reserved
Adv
LP
5
0
0
RPDCTR
Remote
Pardet
Fault
Fault
-EN
4
0
0
Link Partner Protocol Selector Field
Advertised Protocol Selector Field
000_0000
LP Next
Pg Able
St. Mch
Reserved
Auto-N
Reset
Cap.
3
1
0
DM9008AEP
Auto-N. Monitor Bit [3:0]
Version No.
Next Pg
Pream.
Status
Supr.
Able
Link
0000
2
0
0
New Pg
Jabber
Detect
Sleep
mode
Rcv
1
0
0
LP AutoN
LoopOut
Reverse
Remote
Polarity
Extd
Cap.
Cap.
0
1
1
27