DM8603EP DAVICOM [Davicom Semiconductor, Inc.], DM8603EP Datasheet
DM8603EP
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DM8603EP Summary of contents
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DAVICOM Semiconductor, Inc. 10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface Preliminary datasheet DM8603-12-DS-P01 November 8, 2010 10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface DM8603 DATASHEET DM8603 Preliminary Datasheet Version: DM8603-DS-P01 November 8, ...
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GENERAL DESCRIPTION............................................................................................ 8 2. BLOCK DIAGRAM........................................................................................................ 8 3. FEATURES ................................................................................................................... 9 4. PIN CONFIGURATION ............................................................................................... 10 5. PIN DESCRIPTION ..................................................................................................... 11 5.1 P2 MII / Reduce MII / Reverse MII.................................................................................................................. 11 5.1.1 MII ............................................................................................................................................................. 11 5.1.2 Reduce MII................................................................................................................................................ 11 ...
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Switch Registers Map......................................................................................................................................... 25 7.2 Per Port Switch Register.................................................................................................................................... 28 7.2.1 Per Port Status Register (110h, 130h, 150h)........................................................................................... 28 7.2.2 Per Port Basic Control Register 1 (111h, 131h, 151h) ........................................................................... 28 7.2.3 Per Port Basic Control Register 2 (112h, ...
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VLAN Table Register 5 (275h) ................................................................................................................ 51 7.3.27 VLAN Table Register 6 (276h) ................................................................................................................ 51 7.3.28 VLAN Table Register 7 (277h) ................................................................................................................ 51 7.3.29 VLAN Table Register 8 (278h) ................................................................................................................ 52 7.3.30 VLAN Table Register 9 (279h) ................................................................................................................ 52 ...
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Address Learning...................................................................................................................................... 71 9.2.2 Address Aging ........................................................................................................................................... 71 9.2.3 Packet Forwarding ................................................................................................................................... 71 9.2.4 Inter-Packet Gap (IPG)............................................................................................................................ 71 9.2.5 Back-off Algorithm................................................................................................................................... 71 9.2.6 Late Collision ............................................................................................................................................ 72 9.2.7 Full Duplex Flow Control......................................................................................................................... 72 9.2.8 Half Duplex Flow Control........................................................................................................................ 72 ...
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MLT-3 Driver ...................................................................................................................... 89 9.4.1.7 4B5B Code Group ............................................................................................................. 90 9.4.2 100Base-TX Receiver................................................................................................................................ 91 9.4.2.1 Signal Detect ..................................................................................................................... 91 9.4.2.2 Adaptive Equalization....................................................................................................... 91 9.4.2.3 MLT-3 to NRZI Decoder .................................................................................................... 91 9.4.2.4 Clock Recovery Module.................................................................................................... 91 9.4.2.5 NRZI to NRZ ...
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PACKAGE INFORMATION ...................................................................................... 104 13. TERMINOLOGY........................................................................................................ 105 14. ORDERING INFORMATION ..................................................................................... 107 Preliminary datasheet DM8603-12-DS-P01 November 8, 2010 10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface DM8603 7 ...
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General Description The DM8603 is Davicom’s new fully integrated three-port 10M/100Mbps Fast Ethernet Controller fast Ethernet switch, the DM8603 consists of two PHY ports and a third port with either MII or RMII interface. As the DM8603 ...
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Features • IEEE 802.3/u 10Base-T/100Base-TX compatible • Ethernet Switch Ports: o Two 10/100Mbps PHY o One MII/RMII interface with Reversed - MII support • Supports auto crossover function - HP Auto-MDIX • Flow Control o Supports IEEE 802.3x Flow ...
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... Pin Configuration 64 pin LQFP: Preliminary datasheet DM8603-12-DS-P01 November 8, 2010 10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface DM8603EP DM8603 10 ...
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Pin Description I = Input Output Asserted Low PD=internal pull-low (about 50K Ohm) 5.1 P2 MII / Reduce MII / Reverse MII 5.1.1 MII Pin No. Pin Name PHY_MDC 2 3 PHY_MDIO 5 P2_TXD3 P2_TXD2 ...
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Reverse MII Pin No. Pin Name 2 PHY_MDC 3 PHY_MDIO P2_TXD3 5 P2_TXD2 6 P2_TXD1 7 P2_TXD0 9 P2_TXE 10 P2_TXC 12 14 P2_TXER P2_CRS 15 P2_COL 17 18 P2_RXER P2_RXC 19 20 P2_RXDV 21 P2_RXD3 P2_RXD2 22 P2_RXD1 ...
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Clock Interface Pin No. Pin Name 5.5 Network Interface Pin No. Pin Name 34 P1_TX+ 35 P1_TX - 37 P1_RX+ 38 P1_RX- 41 P0_TX+ 42 P0_TX- 44 P0_RX+ 45 P0_RX - 47 BGRES 48 BGGND ...
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Power Pins Pin No. Pin Name 1,13,26,51 DVDD33 11,61 DVDD18 4,8,16,23,31,64 DGND 39,46 AVDD33 33,40 AVDD18 36,43,54 AGND 5.8 Strap Pins Table Pin No. Pin Name 10 P2_TXE Port 2 Force Mode Enable Port 2 Speed Selection in Force ...
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PHY Registers 6.1 PHY Registers Map PHY_ADR REG_ADR ABS_ADR 02h 00h 040h 01h 041h 02h 042h 03h 043h 04h 044h 05h 045h 06h 046h 14h 054h 1Dh 05Dh 03h 00h 060h 01h 061h 02h 062h 03h 063h 04h 064h ...
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Basic Mode Control Register (040h, 060h) PHY_ADR REG_ADR 02h, 03h 00h Bit Bit Name Default 15 Reset RW/SC 14 Loopback RW 13 Speed selection RW 12 Auto-negotiation RW enable 11 Power down RW 10 Isolate RW 9 Restart RW/SC ...
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Collision test RW 6:0 RESERVED RO 6.3 Basic Mode Status Register (041h, 061h) PHY_ADR REG_ADR 02h, 03h 01h Bit Bit Name Default 15 100BASE-T4 RO/P 14 100BASE-TX RO/P full-duplex 13 100BASE-TX RO/P half-duplex 12 10BASE-T RO/P full-duplex 11 10BASE-T ...
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Jabber detect RO 0 Extended RO/P capability Preliminary datasheet DM8603-12-DS-P01 November 8, 2010 10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface cleared and remain cleared until it is read via the management interface Valid ...
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PHY ID Identifier Register 1 (042h, 062h) PHY_ADR REG_ADR 02h, 03h 02h Bit Bit Name Default 15:0 OUI_MSB RO 0181h The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM8603. The Identifier consists ...
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Auto-negotiation Advertisement Register (044h, 064h) PHY_ADR REG_ADR 02h, 03h 04h Bit Bit Name Default 15 NP RO/P 14 ACK 12:11 RESERVED RW 00b 10 FCS RO/P 8 TX_FDX RW 7 TX_HDX RW ...
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Auto-negotiation Link Partner Ability Register (045h, 065h) PHY_ADR REG_ADR 02h, 03h 05h Bit Bit Name Default ACK 12:11 RESERVED RO 00b 10 FCS TX_FDX RO 7 ...
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Auto-negotiation Expansion Register (046h, 066h) PHY_ADR REG_ADR 02h, 03h 06h Bit Bit Name Default 15:5 RESERVED RO 4 PDF RO/LH 3 LP_NP_ABLE RO 2 NP_ABLE RO/P 1 PAGE_RX RO 0 LP_AN_ABLE RO Preliminary datasheet DM8603-12-DS-P01 November 8, 2010 10/100 ...
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Specified Configuration Register (054h, 074h) PHY_ADR REG_ADR 02h, 03h 14h Bit Bit Name Default 15:12 RESERVED RW 0000b RW 11 PREAMBLEX RW 10 TX10M_PWR RW 9 NWAY_PWR 8 RESERVED RO 7 MDIX_CNTL RO 6 RESERVED RW 5 Mdix_fix Value ...
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Power Saving Control Register (05Dh, 07Dh) PHY_ADR REG_ADR 02h, 03h 1Dh Bit Bit Name Default 15:12 RESERVED RO 0000b 11 PREAMBLEX RW 10 RESERVED RW 9 TX_PWR RW 8:0 RESERVED RO Preliminary datasheet DM8603-12-DS-P01 November 8, 2010 10/100 Mbps ...
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Switch Registers 7.1 Switch Registers Map PHY_ADR REG_ADR ABS_ADR 08h 00h~0Fh 100h~10Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah~1Fh 11Ah~11Fh 09h 00h~0Fh 120~12F 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah~1Fh 13Ah~13Fh ...
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13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 11h 00h~0Fh 220h~22Fh 10h 11h 12h 13h 14h~1Dh 234h~23Dh 1Eh 1Fh 13h 00h~0Fh 260h~26Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch ...
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Key to Default ...
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Per Port Switch Register 7.2.1 Per Port Status Register (110h, 130h, 150h) PHY_ADR REG_ADR 08h, 09h, 0Ah 10h Bit ROM Type 15:5 --- RO 4 --- --- RO 2 --- --- P, RO ...
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PSE,RW 90h.[11] A0h.[11] 10 --- RO 9 80h.[9] PSE,RW 90h.[9] A0h.[9] 8 80h.[8] PSE,RW 90h.[8] A0h.[8] 7 80h.[7] PSE,RW 90h.[7] A0h.[7] 6 80h.[6] PSE,RW 90h.[6] A0h.[6] 5 80h.[5] PSE,RW 90h.[5] A0h.[5] 4 80h.[4] PSE,RW 90h.[4] A0h.[4] 3:2 80h.[3:2] ...
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Per Port Basic Control Register 2 (112h, 132h, 152h) PHY_ADR REG_ADR 08h, 09h, 0Ah 12h Bit ROM Type 15 81h.[15] PSE,RW 91h.[15] A1h.[15] 14 81h.[14] PSE,RW 91h.[14] A1h.[14] 13 81h.[13] PSE,RW 91h.[13] A1h.[13] 12 81h.[12] PSE,RW 91h.[12] A1h.[12] 11 ...
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RO 2 81h.[2] PSE,RW 91h.[2] A1h.[2] 1 --- RO 0 81h.[0] PSE,RW 91h.[0] A1h.[0] 7.2.4 Per Port Block Control Register 1 (113h, 133h, 153h) PHY_ADR REG_ADR 08h, 09h, 0Ah 13h Bit ROM Type 15:11 --- RO 10:8 82h.[10:8] ...
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Per Port Block Control Register 2 (114h, 134h, 154h) PHY_ADR REG_ADR 08h, 09h, 0Ah 14h Bit ROM Type 15:11 --- RO 10:8 83h.[10:8] PSE,RW 93h.[10:8] A3h.[10:8] 7:3 --- RO 2:0 83h.[2:0] PSE,RW 93h.[2:0] A3h.[2:0] Preliminary datasheet DM8603-12-DS-P01 November 8, ...
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Per Port Bandwidth Control Register (115h, 135h, 155h) PHY_ADR REG_ADR 08h, 09h, 0Ah 15h Bit ROM Type 15:12 84h.[15:12] PSE,RW 94h.[15:12] A4h.[15:12] 11:8 84h.[11:8] PSE,RW 94h.[11:8] A4h.[11:8] Preliminary datasheet DM8603-12-DS-P01 November 8, 2010 10/100 Mbps 3-port Ethernet Switch Controller ...
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PSE,RW 94h.[7:4] A4h.[7:4] 3:0 84h.[3:0] PSE,RW 94h.[3:0] A4h.[3:0] Preliminary datasheet DM8603-12-DS-P01 November 8, 2010 10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface 0000b BSTH[3:0] Broadcast Storm Threshold These bits define the bandwidth threshold that received ...
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Per Port VLAN Tag Register (116h, 136h, 156h) PHY_ADR REG_ADR 08h, 09h, 0Ah 16h Bit ROM Type 15:13 85h.[15:13] PSE,RW 95h.[15:13] A5h.[15:13] 12 85h.[12] PSE,RW 95h.[12] A5h.[12] 11:0 85h.[11:0] PSE,RW 95h.[11:0] A5h.[11:0] 7.2.8 Per Port Priority & VLAN Control ...
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PSE,RW 96h.[6] A6h.[6] 5 86h.[5] PSE,RW 96h.[5] A6h.[5] 4 86h.[4] PSE,RW 96h.[4] A6h.[4] 3 86h.[3] PSE,RW 96h.[3] A6h.[3] 2 86h.[2] PSE,RW 96h.[2] A6h.[2] 1:0 86h.[1:0] PSE,RW 96h.[1:0] A6h.[1:0] Preliminary datasheet DM8603-12-DS-P01 November 8, 2010 10/100 Mbps 3-port Ethernet ...
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Per Port Advanced Control Register (119h, 139h, 159h) PHY_ADR REG_ADR 08h, 09h, 0Ah 19h Bit ROM Type 15:9 --- RO 8 88h.[8] PSE,RW 98h.[8] A8h.[8] 7:2 --- RO 1:0 --- PS,RW Preliminary datasheet DM8603-12-DS-P01 November 8, 2010 10/100 Mbps ...
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Global Switch Register 7.3.1 Switch Status Register (210h) PHY_ADR REG_ADR 10h 10h Bit ROM Type 15:2 --- RO 1 --- PS --- PS, RO 7.3.2 Switch Reset Register (211h) PHY_ADR REG_ADR 10h 11h Bit ROM Type 15:3 ...
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Switch Control Register (212h) PHY_ADR REG_ADR 10h 12h Bit ROM Type 15:6 --- RO 5 12h.[5] PSE,RW 4:3 --- RO 2 12h.[2] PSE,RW 1:0 --- RO 7.3.4 Mirror Control Register (213h) PHY_ADR REG_ADR 10h 13h Bit ROM Type 15:11 ...
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PSE, RW 2:0 --- RO 7.3.5 Special Tag Ether-Type Register (214h) PHY_ADR REG_ADR 10h 14h Bit ROM Type 15:0 PSE,RW 14h 7.3.6 Global Learning & Aging Control Register (215h) PHY_ADR REG_ADR 10h 15h Bit ROM Type 15:6 --- ...
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VLAN Priority Map Register (217h) PHY_ADR REG_ADR 10h 17h Bit ROM Type 15:14 1Ch.[15:14] PSE,RW 13:12 1Ch.[13:12] PSE,RW 11:10 1Ch.[11:10] PSE,RW 9:8 1Ch.[9:8] PSE,RW 7:6 1Ch.[7:6] PSE,RW 5:4 1Ch.[5:4] PSE,RW 3:2 1Ch.[3:2] PSE,RW 1:0 1Ch.[1:0] PSE,RW 7.3.8 TOS Priority ...
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TOS Priority Map Register 2 (219h) PHY_ADR REG_ADR 10h 19h Bit ROM Type 15:14 1Eh.[15:14] PSE,RW 13:12 1Eh.[13:12] PSE,RW 11:10 1Eh.[11:10] PSE,RW 9:8 1Eh.[9:8] PSE,RW 7:6 1Eh.[7:6] PSE,RW 5:4 1Eh.[5:4] PSE,RW 3:2 1Eh.[3:2] PSE,RW 1:0 1Eh.[1:0] PSE,RW 7.3.10 TOS ...
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TOS Priority Map Register 4 (21Bh) PHY_ADR REG_ADR 10h 1Bh Bit ROM Type 15:14 20h.[15:14] PSE,RW 13:12 20h.[13:12] PSE,RW 11:10 20h.[11:10] PSE,RW 9:8 20h.[9:8] PSE,RW 7:6 20h.[7:6] PSE,RW 5:4 20h.[5:4] PSE,RW 3:2 20h.[3:2] PSE,RW 1:0 20h. [1:0] PSE,RW 7.3.12 ...
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TOS Priority Map Register 6 (21Dh) PHY_ADR REG_ADR 10h 1Dh Bit ROM Type 15:14 22h.[15:14] PSE,RW 13:12 22h.[13:12] PSE,RW 11:10 22h.[11:10] PSE,RW 9:8 22h.[9:8] PSE,RW 7:6 22h.[7:6] PSE,RW 5:4 22h.[5:4] PSE,RW 3:2 22h.[3:2] PSE,RW 1:0 22h.[1:0] PSE,RW 7.3.14 TOS ...
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TOS Priority Map Register 8 (21Fh) PHY_ADR REG_ADR 10h 1Fh Bit ROM Type 15:14 24h.[15:14] PSE,RW 13:12 24h.[13:12] PSE,RW 11:10 24h.[11:10] PSE,RW 9:8 24h.[9:8] PSE,RW 7:6 24h.[7:6] PSE,RW 5:4 24h.[5:4] PSE,RW 3:2 24h.[3:2] PSE,RW 1:0 24h.[1:0] PSE,RW Preliminary datasheet ...
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MIB Counter Disable Register (230h) PHY_ADR REG_ADR 11h 10h Bit ROM Type 15:3 --- RO 2:0 16h.[2:0] PSE,RW 7.3.17 MIB Counter Control Register (231h) PHY_ADR REG_ADR 11h 11h Bit ROM Type 15 --- PS,RO 14:10 --- RO 9:8 --- ...
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MIB Counter Data Register 1 (232h) PHY_ADR REG_ADR 11h 12h Bit ROM Type 15:0 --- PS,RW 7.3.19 MIB Counter Data Register 2 (233h) PHY_ADR REG_ADR 11h 13h Bit ROM Type 15:0 --- PS,RW MIB Counter (OFFSET 00h): RX Byte ...
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VLAN Mode & Rule Control Register (23Eh) PHY_ADR REG_ADR 11h 1Eh Bit ROM Type 15 31h.[15] PSE,RW 14 31h.[14] PSE,RW 13:9 --- RO 8 31h.[8] PSE,RW 7 31h.[7] PSE,RW 6 --- RO 5 31h.[5] PSE,RW 4 31h.[4] PSE,RW 3 ...
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PSE,RW 0 31h.[0] PSE,RW Preliminary datasheet DM8603-12-DS-P01 November 8, 2010 10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface 0b VLAN_RPRI Replace VLAN Priority Replace the received 08h/09h/0Ah.16h.[15:13] 0: Disable 1: Enable VLAN Mode Selection 0b ...
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VLAN Table Register 0 (270h) PHY_ADR REG_ADR 13h 10h Bit ROM Type 15:3 --- RO 2:0 43h.[2:0] PSE,RW 7.3.22 VLAN Table Register 1 (271h) PHY_ADR REG_ADR 13h 11h Bit ROM Type 15:3 --- RO 2:0 44h.[2:0] PSE,RW 7.3.23 VLAN ...
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VLAN Table Register 4 (274h) PHY_ADR REG_ADR 13h 14h Bit ROM Type 15:3 --- RO 2:0 47h.[2:0] PSE,RW 7.3.26 VLAN Table Register 5 (275h) PHY_ADR REG_ADR 13h 15h Bit ROM Type 15:3 --- RO 2:0 48h.[2:0] PSE,RW 7.3.27 VLAN ...
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VLAN Table Register 8 (278h) PHY_ADR REG_ADR 13h 18h Bit ROM Type 15:3 --- RO 2:0 4Bh.[2:0] PSE,RW 7.3.30 VLAN Table Register 9 (279h) PHY_ADR REG_ADR 13h 19h Bit ROM Type 15:3 --- RO 2:0 4Ch.[2:0] PSE,RW 7.3.31 VLAN ...
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VLAN Table Register 12 (27Ch) PHY_ADR REG_ADR 13h 1Ch Bit ROM Type 15:3 --- RO 2:0 4Fh.[2:0] PSE,RW 7.3.34 VLAN Table Register 13 (27Dh) PHY_ADR REG_ADR 13h 1Ch Bit ROM Type 15:3 --- RO 2:0 50h.[2:0] PSE,RW 7.3.35 VLAN ...
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STP Control Register (292h) PHY_ADR REG_ADR 14h 12h Bit ROM Type 15:1 --- RO 0 --- PS,RW 7.3.38 Snooping Control Register 1 (29Bh) PHY_ADR REG_ADR 14h 1Bh Bit ROM Type 15:11 --- RO 10:8 17h.[10:8] PSE,RW 7 17h. [8] ...
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PSE,RW 7.3.39 Snooping Control Register 2 (29Ch) PHY_ADR REG_ADR 14h 1Ch Bit ROM Type 15:13 --- RO 12 18h.[12] PSE,RW 11:10 18h. [11:10] PSE,RW 9:8 18h. [9:8] PSE,RW 7:0 18h. [7:0] PSE,RW Preliminary datasheet DM8603-12-DS-P01 November 8, ...
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Address Table Control & Status Register (2B0h) PHY_ADR REG_ADR 15h 10h Bit ROM Type 15 --- PS,RO 14:13 --- PS,RW 12:5 --- RO 4:2 --- PS,RW 1:0 --- PS,RW Preliminary datasheet DM8603-12-DS-P01 November 8, 2010 10/100 Mbps 3-port Ethernet ...
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Address Table Data Register 1 (2B1h) PHY_ADR REG_ADR 15h 11h Bit ROM Type 15:3 --- RO 2:0 --- PS,RW 7.3.42 Address Table Data Register 2 (2B2h) PHY_ADR REG_ADR 15h 12h Bit ROM Type 15:0 --- PS,RW 7.3.43 Address Table ...
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PHY_ADR REG_ADR 18h 10h Bit ROM Type 15:0 04H.[15:0] PE,RO 7.3.47 Product ID Register (311h) PHY_ADR REG_ADR 18h 11h Bit ROM Type 15:0 05h.[15:0] PE,RO Preliminary datasheet DM8603-12-DS-P01 November 8, 2010 10/100 Mbps 3-port Ethernet Switch Controller with MII / ...
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Port 2 MAC Control Register (315h) PHY_ADR REG_ADR 18h 15h Bit ROM Type 15:10 --- RO 9:8 0Dh.[9:8] PE,RW 7:4 --- RO 3 0Dh. [3] PSET,RW 2 0Dh. [2] PSE,RW 1 0Dh. [1] PSE,RW 0 0Dh. [0] PSET,RW Preliminary ...
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EEPROM Control & Address Register (31Ah) PHY_ADR REG_ADR 18h 1Ah Bit ROM Type 15:8 --- PS,RW 7 --- RO 6 --- P,RW 5 --- PS,RW 4 --- PS,RW 3 --- PS,RW 2 --- PS,RW 1 --- PS,RW 0 --- ...
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Strap Pin Control & Status Register (31Ch) PHY_ADR REG_ADR 18h 1Ch Bit ROM Type 15 --- PT,RO 14 --- PT,RO 13 --- PT,RO 12 --- RW 11 --- RO 10 --- PT,RO 9 --- PT,RO 8:6 --- RO 5 ...
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SMI Bus Error Check Register (339h) PHY_ADR REG_ADR 19h 19h Bit ROM Type 15 --- PS,RO 7:0 --- PS,RW 7.3.53 SMI Bus Control Register (33Ah) PHY_ADR REG_ADR 19h 1Ah Bit ROM Type 15:1 --- RO 0 ...
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PHY Control Register (33Eh) PHY_ADR REG_ADR 19h 1Eh Bit ROM Type 15 07h.[15] PSE,RW 14 07h. [14] PSE,RW 13:9 --- RO 8 07h. [8] PSET,RW 7:4 --- RO 3:0 --- PS,RW Note: There are two method to control Auto-MDIX ...
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EEPROM Format Name Word Signature 00h RESERVED 01h~02h Load Control 0 03h Vendor ID 04h Product ID 05h RESERVED 06h PHY control 07h RESERVED 08h PHY Vendor ID 09h PHY Device ID 0Ah RESERVED 0Bh~0Ch Port 2 MAC Control ...
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Load Control 1 0Eh Load Control 2 0Fh RESERVED 10h~11h Switch Control 12h Mirror Control 13h Special Tag Ether-Type 14h Global Learning & 15h Aging Control MIB Counter Disable 16h Snoop Ctrl 0 17h Snoop Ctrl 1 18h RESERVED 19h~1Bh ...
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TOS Priority Map 0 1Dh TOS Priority Map 1 1Eh TOS Priority Map 2 1Fh TOS Priority Map 3 20h TOS Priority Map 4 21h TOS Priority Map 5 22h TOS Priority Map 6 23h TOS Priority Map 7 24h ...
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MEMBER_FH RESERVED 53h~7Fh P0 Basic Control 0 80h P0 Basic Control 1 81h P0 Block Control 0 82h P0 Block Control 1 83h P0 Bandwidth Control 84h P0 VLAN Tag 85h Information P0 Priority & VLAN 86h Control RESERVED 87h ...
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P2 Block Control 1 A3h P2 Bandwidth Control A4h P2 VLAN Tag A5h Information P2 Priority & VLAN A6h Control RESERVED A7h P2 Advanced Control A8h RESERVED A9h~AAh RESERVED ABh~FFh Preliminary datasheet DM8603-12-DS-P01 November 8, 2010 10/100 Mbps 3-port Ethernet ...
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Functional Description 9.1 Host Serial Management Interface 9.1.1 Host SMI Frame Structure Host SMI - Read Frame Structure Host SMI - Write Frame Structure The Host SMI consists of two pins, one is SMI_MDC and another is SMI_MDIO. User ...
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Host SMI Bus Error Check Function Because SMI bus tends to be interfered by noise on board-level. This function is used to check the command validity to suppress the mistaken command. In write procedure, the written value in register ...
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Switch Functions 9.2.1 Address Learning The DM8603 has a self-learning mechanism for learning the MAC addresses of incoming packets in real time. DM8603 stores MAC addresses, port number and time stamp information in the Hash-based Address Table. It can ...
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Late Collision Late Collision is a type of collision collision error occurs after the first 512 bit times of data are transmitted, the packet is dropped. 9.2.7 Full Duplex Flow Control The DM8603 supports IEEE standard 802.3x ...
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Broadcast Storm Filtering The DM8603 has an option to limit the traffic of broadcast or multicast packets, to protect the switch from lower bandwidth availability. There are two types of broadcast storm control, one is throttling broadcast packet only, ...
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VLAN Support 9.2.13.1 Port-Based VLAN The DM8603 supports port-based VLAN as default, and groups. Each port has a default VID called PVID (Port VID, see REG 08h/09h/0Ah.16h). For VLAN setting, the DM8603 used LSB 4-bytes of ...
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Special Tag The Special Tag function provided by the DM8603 is used to exchange control and status information between Switch and CPU within frame. An extra 4-bytes tag is added into frame to carry different content according to direction ...
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Received Special Tag(CPU Switch) 4-byte Format: Byte 0/1: [15:0] Special Tag Ether-Type (Default: 0x8086) Byte 2: [7] Reserved [6] ST_PMAP_en, ST_PMAP Enable [5:3] Reserved [2:0] ST_PMAP, Force to assign forwarding port map Byte 3: [7] Reserved [6] ST_CVLAN, Cross VLAN ...
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Priority Support The DM8603 supports Quality of Service (QoS) mechanism for multimedia communication such as VoIP and video conferencing. The DM8603 provides three priority classifications: Port-based, 802.1p-based and DiffServ-based priority. See next section for more detail. The DM8603 offers ...
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Address Table Accessing 9.2.16.1 Type of Address Table There are three types of address table in the DM8603. The description is represented below: (1). Unicast Address Table This table is used for destination MAC address lookup and source MAC ...
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Check the busy bit again, wait for available. (5). Read the command status from Address Table Control & Status Register (REG 15h.10h.[14:13]). Entry Search (1). Check the busy bit of Address Table Control & Status Register (REG 15h.10h.[15]) to ...
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Preliminary datasheet DM8603-12-DS-P01 November 8, 2010 10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface DM8603 80 ...
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Preliminary datasheet DM8603-12-DS-P01 November 8, 2010 10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface DM8603 81 ...
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IGMP Snooping The Internet Group Management Protocol (IGMP communications protocol used to manage the membership of Internet Protocol multicast groups. IGMP is used by IP hosts and adjacent multicast routers to establish multicast group memberships. There are ...
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STP / RSTP Support DM8603 supports both Spanning Tree Protocol (STP) and Rapid Spanning Tree Protocol (RSTP). There are five types of STP Port State (Disabled, Blocking, Listening, Learning and Forwarding state) and three types of RSTP Port State ...
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Disable State: Drop all packets including BPDUs Implemented by transmitting BPDUs to CPU and CPU drops BPDUs. Learning is disabled. Does not transmit BPDUs received from CPU Implemented by CPU does not send BPDUs to this port (2). Blocking ...
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The following flow diagram shows how to configure STP/RSTP function. Set REG 14h.12h.[0] to REG 08h/09h/0A h.19h.[1: Setting Preliminary datasheet DM8603-12-DS-P01 November 8, 2010 10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface Start ...
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MII Interface 9.3.1 MII Data Interface The DM8603 port 2 provides a Media Independent Interface (MII) as defined in the IEEE 802.3u standard (Clause 22). The MII consists of a nibble wide receive data bus, a nibble wide transmit ...
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MII Serial Management Interface The serial control interface uses a simple two-wired serial interface to obtain and control the status of the physical layer through the MII interface. The serial control interface consists of PHY_MDC (Management Data Clock to ...
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Internal PHY Functions 9.4.1 100Base-TX Operation The transmitter section contains the following functional blocks: 4B5B Encoder Scrambler Parallel to Serial Converter NRZ to NRZI Converter NRZI to MLT-3 MLT-3 Driver 9.4.1.1 4B5B Encoder The 4B5B encoder converts 4-bit (4B) ...
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One event. 9.4.1.6 MLT-3 Driver The two binary data streams created at the MLT-3 converter are fed to the twisted pair output driver, which converts these streams to current sources and ...
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Code Group Symbol Preliminary datasheet DM8603-12-DS-P01 ...
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Receiver The 100Base-TX receiver contains several function blocks that convert the scrambled 125Mb/s serial data to synchronous 4-bit nibble data. The receive section contains the following functional blocks: Signal Detect Digital Adaptive Equalization MLT-3 to Binary Decoder Clock ...
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NRZI to NRZ The transmit data stream is required to be NRZI encoded for compatibility with the TP-PMD standard for 100Base-TX transmission over Category-5 unshielded twisted pair cable. This conversion process must be reversed on the receive end. The ...
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Operation The 10Base-T transceiver is IEEE 802.3u compliant. When the DM8603 is operating in 10Base-T mode, the coding scheme is Manchester. Data processed for transmit is presented in nibble format, converted to a serial bit stream, then the ...
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LFP and FEF Function The DM8603 pairs Port 0 and Port 1 for media converter application and supports LFP (Link Fault Pass-through) and FEF (Far End Fault) troubleshooting features. The LFP (Link Fault Pass-through) allows the DM8603 to monitor ...
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DC and AC Electrical Characteristics 10.1 Absolute Maximum Ratings Symbol DVDD33 Digital 3.3V Power DVDD18 Digital 1.8V Power AVDD33 Analog 3.3V Power AVDD18 Analog 1.8V Power IOV Input/Output Voltage Storage Temperature Range T STG Ambient Temperature T A Lead ...
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DC Electrical Characteristics Symbol Parameter Inputs VIL Input Low Voltage VIH Input High Voltage IIL Input Low Leakage Current IIH Input High Leakage Current Outputs VOL Output Low Voltage VOH Output High Voltage Receiver VICM RX+/RX- Common Mode Input ...
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AC Characteristics 10.4.1 Power On Reset Timing Symbol Parameter T1 PWRST# Low Period T2 Strap pin hold time with PWRST# T3 PWRST# high to EECS high T4 PWRST# high to EECS burst end Preliminary datasheet DM8603-12-DS-P01 November 8, 2010 ...
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Port 2 MII Interface Transmit Timing Symbol T1 100M MII Transmit Clock Period T1 10M MII Transmit Clock Period T2 P2_TXE,P2_TXD3~0 to P2_TXC Rising Output Delay 10.4.3 Port 2 MII Interface Receive Timing Symbol T1 100M MII Receive Clock ...
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Port 2 RMII Interface Transmit Timing Symbol T1 RMII REF_CLK Period T2 P2_TXE,P2_TXD1~0 to REF_CLK Rising Output Delay 10.4.5 Port 2 RMII Interface Receive Timing Symbol T1 RMII REF_CLK Period T2 CRS_DV, P2_RXD to REF_CLK Setup Time T3 CRS_DV, ...
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MII Management Interface Timing Symbol T1 PHY_MDC Period T2 PHY_MDIO to PHY_MDC Setup Time on Input State T3 PHY_MDIO to PHY_MDC Hold Time on Input State T4 PHY_MDIO to PHY_MDC Rising Output Delay on Output State 10.4.7 Host SMI ...
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EEPROM Timing Symbol T1 EECK Period T2 EECS to EECK Rising Output Delay T3 EEDIO to EECK Rising Output Delay on Output State T4 EEDIO to EECK Rising Setup Time on Input State T5 EEDIO to EECK Rising Hold ...
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Application Information 11.1 Application of Reverse MII RevMII MAC I/F SMI_MDC SMI_MDIO PHY_MDC PHY_MDIO P2_RXC P2_TXC P2_TXD3~0 P2_TXE P2_RXD3~0 P2_RXDV P2_CRS P2_COL P2_RXER P2_TXER Note: The P2_TXE and P2_TXD2 pins of DM8603 must be pull-up resistor with 4.7K ohm ...
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Application of Reduce MII to PHY RMII MAC I/F NC SMI_MDC NC NC SMI_MDIO PHY_MDC PHY_MDIO P2_TXD1~0 P2_TXE P2_RXD1~0 P2_CRS P2_RXC P2_TXC Reference Clock Note: The P2_TXD3 pin of DM8603 must be pull-up resistor with 4.7K ohm to DVDD33 ...
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Package Information 64 Pins LQFP Package Outline Information: Symbol θ θ 1 θ ...
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Terminology B BIST Built-in Self-Test BPDU Bridge Protocol Data Unit Byte 8-bits C CFI Canonical Format Indicator COL Collision CRC Cyclic Redundancy Check CRS Carrier Sense CSR Control and Status Registers D DMAC Destination MAC Address E ESD End ...
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QoS Quality of Service R REG Register RevMII Reversed MII RMII Reduce MII RSTP IEEE 802.1w - Rapid Spanning Tree Protocol S SFD Start of Frame Delimiter SMAC Source MAC Address SMI Serial Management Interface STP IEEE 802.1D - Spanning ...
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... Ordering Information Part Number Pin Count DM8603EP 64 Disclaimer The information appearing in this publication is believed to be accurate. Integrated circuits sold by DAVICOM Semiconductor are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. DAVICOM makes no warranty, express, statutory, implied or by description regarding the information in this ...