DM8603EP DAVICOM [Davicom Semiconductor, Inc.], DM8603EP Datasheet - Page 86

• Manufacturer Part Number: DM8603EP
• Description: 10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
• Manufacturer: DAVICOM [Davicom Semiconductor, Inc.]

9.3 MII Interface
9.3.1
(Clause 22).
facilitate data transfers between the DM8603 port 2 and external device (a PHY or a MAC in reverse MII).
Preliminary datasheet
DM8603-12-DS-P01
November 8, 2010
The DM8603 port 2 provides a Media Independent Interface (MII) as defined in the IEEE 802.3u standard
The MII consists of a nibble wide receive data bus, a nibble wide transmit data bus, and control signals to
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MII Data Interface
P2_TXD3~0 (transmit data) is a nibble (4 bits) of data that are driven by the DM8603 synchronously
with respect to P2_TXC. For each P2_TXC period, which P2_TXE is asserted, P2_TXD3~0 are
accepted for transmission by the external device.
P2_TXC (transmit clock) from the external device is a continuous clock that provides the timing
reference for the transfer of the P2_TXE, P2_TXD3~0. The DM8603 can drive 25MHz clock if it is
configured to reversed MII mode.
P2_TXE (transmit enable) from the DM8603 port 2 MAC indicates that nibbles are being presented
on the MII for transmission to the external device.
P2_RXD3~0 (receive data) is a nibble (4 bits) of data that are sampled by the DM8603 port 2 MAC
synchronously with respect to P2_RXC. For each P2_RXC period which P2_RXDV is asserted,
P2_RXD3~0 are transferred from the external device to the DM8603 port 2 MAC reconciliation sub
layer.
P2_RXC3~0 (receive clock) from external device to the DM8603 port 2 MAC reconciliation sub layer
is a continuous clock that provides the timing reference for the transfer of the P2_RXDV,
P2_RXD3~0, and P2_RXER signals.
P2_RXDV (receive data valid) input from the external device to indicates that the external device is
presenting recovered and decoded nibbles to the DM8603 port 2 MAC reconciliation sub layer. To
interpret a receive frame correctly by the reconciliation sub layer, P2_RXDV must encompass the
frame, starting no later than the Start-of-Frame delimiter and excluding any End-Stream delimiter.
P2_RXER (receive error) input from the external device is synchronously with respect to P2_RXC.
P2_RXER will be asserted for 1 or more clock periods to indicate to the reconciliation sub layer that
an error was detected somewhere in the frame being transmitted from the external device to the
DM8603 port 2 MAC.
P2_CRS (carrier sense) is asserted by the external device when either the transmit or receive
medium is non-idle, and de-asserted by the external device when the transmit and receive medium
are idle. The P2_CRS can also in output mode when the DM8603 port 2 is configured to reversed
MII mode.
P2_COL (collision detection) is asserted by the external device, when both the transmit and receive
medium is non-idle, and de-asserted by the external device when the either transmit or receive
medium are idle. The P2_COL can also in output mode when the DM8603 port 2 is configured to
reversed MII mode.
10/100 Mbps 3-port Ethernet Switch Controller with MII / RMII Interface
DM8603
86