DM9801AE Davicom Semiconductor, Inc., DM9801AE Datasheet
DM9801AE
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DM9801AE Summary of contents
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General Description The DM9801A is a physical-layer, single-chip, low-power transceiver for 1M Home Phoneline Network applications. On the media side, it provides an interface to a Home Phoneline wiring system. The reconciliation layer interfaces to the DM9801A either through an ...
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Features • 1M Home Phoneline Network physical-layer, single- chip transceiver • Compatible with HomePNA 1M PHY specification version 1.1 and HomePNA certification document version 1.0 • Supports the MII including the MDIO/MDC serial management interface • Supports the GPSI including ...
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Pin Configuration: DM9801A, 100-pin LQFP DVCC INT# 7 LNKSTA 8 PHYAD1 9 PHYAD2 10 PHYAD3 11 COLLED# 12 RXLED#(LNKLED#) 13 TXLED#(ACTLED#) 14 DGND ...
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Pin Description Pin No. Pin Name I/O Station Interface: Receive Data, Transmit Data and Management 85 TXD0 I or STXDAT 84 TXD1 I or BP1 83 TXD2 TXD3 I or SMODE 86 TX_CLK O,Z or STDCLK ...
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Pin Description (Continued) Pin No. Pin Name I/O Station Interface: Receive Data, Transmit Data and Management (Continued) 67 MDIO I/O,Z Or SCS# 97 RXD0 O,Z Or SRXDAT 96 RXD1 O,Z 95 RXD2 O,Z 94 RXD3 O,Z 90 RX_CLK O,Z Or ...
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Pin Description (Continued) PHY Address Interface: PHYAD[4:0] provides unique PHY address. An address selection of all zeros (00000) will result in a PHY isolation condition. See the isolate bit description in the BMCR, address 00. 68 PHYADSEL ...
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INTFSEL I 60 CMDENA I 59 SPDSEL I 58 PWRSEL I 65 TRIDRV I 57 FWENA I 6 INT# OD Final Version: DM9801A-DS-F01 May 30, 2001 1M Home Phoneline Network Physical Layer Single Chip Transceiver CONFI CONFI G1 G0 ...
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Pin Description (Continued) Pin No. Pin Name I/O LED Interface : These outputs can directly drive LEDs or provide status information to a network management device. 13 TXLED ACTLED# 12 RXLED LNKLED# 11 COLLED# OD Home ...
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Pin Description (Continued) Pin No. Pin Name I/O Miscellaneous: 7 LNKSTA I/O,Z 45 XTAL1 ALG 46 XTAL2 ALG 21 BGREF ALG 22 BGGND ALG 53 TSTMODE 3,5, 15 – 18, 20, 23 – 27 ...
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Functional Description The DM9801A is a single-chip Home Phoneline Network transceiver .The DM9801A provides an IEEE 802.3u subset Media Independent Interface (MII pseudo- standard General Purpose Serial Interface (GPSI). Muxed GPSI or MII Interface MII Interface The DM9801A ...
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MII Interface (continued) RXD (receive data nibble (4 bits) of data that are sampled by the reconciliation sublayer synchronously with respect to RX_CLK. For each RX_CLK period that RX_DV is asserted, RXD (3:0) are transferred from the PHY ...
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MII Interface Transmit and Receive Timing Diagram (continued) TX_CLK TX_EN TXD RX_CLK CRS RXD RX_DV COL RX_CLK becomes disabled (and left in the low state) as soon as CRS is asserted. The clock is re-enabled about 140 uS into the ...
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MII Interface Transmit and Receive Timing Diagram (continued) TX_CLK TX_EN 5 (Preamble) TXD 0 RX_CLK CRS RXD RX_DV COL Once TX_EN is asserted, DM9801A stops RX_CLK, asserts CRS, and toggles TX_CLK at 933.3 ns. TX_CLK TX_EN TXD 5 D RX_CLK ...
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MII Interface Transmit and Receive Timing Diagram (continued) TX_CLK TX_EN TXD DATA RX_CLK CRS RXD RX_DV COL Once TX_EN is cleared, the last symbol gets encoded and transmitted, the looped-back data is presented back to the MAC, and CRS falls. ...
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MII Interface Transmit and Receive Timing Diagram (continued) TX_CLK TX_EN TXD RX_CLK CRS RXD RX_DV COL COL may be asserted up to 120 us after CRS has been asserted. Once COL has been asserted, TX_CLK and RX_CLK run at a ...
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General Purpose Serial Interface The DM 9801 provides a subset Media Independent Interface (MII pseudo-standard General Purpose Serial Interface (GPSI). The GPSI interface provides a simple, easy way to implement connection between the MAC Reconciliation layer and the ...
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General Purpose Serial Interface (continued) STDCLK STXEN STXDAT SRDCLK CRS SRXDAT CLSN SRDCLK becomes disabled as soon as CRS is asserted. STDCLK STXEN STXDAT SRDCLK CRS SRXDAT CLSN SRDCLK and STDCLK are unrelated to each other during this time. When ...
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General Purpose Serial Interface (continued) STDCLK STXEN STXDAT SRDCLK CRS SRXDAT CLSN Once STXEN is asserted, the DM9801A stops SRDCLK, asserts CRS, and toggles STDCLK. STDCLK STXEN STXDAT SRDCLK CRS SRXDAT CLSN STDCLK continues to toggle until SFD is observed, ...
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General Purpose Serial Interface (continued) STDCLK STXEN STXDAT SRDCLK CRS SRXDAT CLSN Once STXEN is cleared, the last symbol gets encoded and transmitted. The looped-back data is presented back to the MAC and sometime later CRS falls. Once CRS falls, ...
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General Purpose Serial Interface (continued) STDCLK STXEN STXDAT SRDCLK CRS SRXDAT CLSN CLSN may be asserted up to 120us after CRS has been asserted. Once CLSN has been asserted STDCLK and SRDCLK run at a period of 233.3ns per cycle ...
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Serial Peripheral Interface (SPI) Bus When INTFSEL is asserted, the DM9801A is configured to operate in SPI mode. While configured to operate in SPI mode, the DM9801A can act as a SPI Slave or SPI Master. Asserting SMODE places the ...
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Serial Peripheral Interface (SPI) Bus (continued) SCLK SCS# SO Instruction Byte SI SCLK SCS ...
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MII and GM_Mode Serial Management Register Map Register Register Name Address 0 BMCR 1 BMSR 2 PHYIDR1 3 PHYIDR2 4 ANAR 5 ANLPAR 6 ANER 16 CNTRL 17 STATUS 18 IMASK 19 ISTAT 20 TX_PCOM_HI 21 TX_PCOM_LO 22 RX_PCOM_HI 23 ...
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Basic Mode Control Register (BMCR) - Register 0 Bit Bit Name 0.15 Reset 0.14 Loopback 0.13 Speed Selection 0.12 Auto-negotiation Enable 0.11 Power Down 0.10 Isolate 0.9 Restart Auto- negotiation 0.8 Duplex Mode 0.7 Collision Test 0.6-0.0 Reserved 24 1M ...
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Basic Mode Status Register (BMSR) - Register 1 Bit Bit Name 1.15 100Base-T4 1.14 100Base-TX Full Duplex 1.13 100Base-TX Half Duplex 1.12 10Base-T Full Duplex 1.11 10Base-T Half Duplex 1.10-1.7 Reserved 1.6 MF Preamble Suppression 1.5 Auto-negotiation Complete 1.4 Remote ...
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Bit Bit Name 2.15-2.0 OUI_MSB PHY Identifier Register #2 (PHYIDR2) - Register 3 Bit Bit Name 3.15-3.10 OUI_LSB <101110>,RO/P 3.9-3.4 VNDR_MDL <010000>,RO/P 3.3-3.0 MDL_REV Auto-negotiation Advertisement Register(ANAR) - Register 4 This register contains the advertised abilities of the DM9801A device ...
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Auto-negotiation Advertisement Register(ANAR) - Register 4 (continued) Bit Bit Name 4.6 10_FDX 4.5 10_HDX 4.4-4.0 Selector <00001>, RO/P Auto-negotiation Link Partner Ability Register (ANLPAR) - Register 5 This register contains the advertised abilities of the link partner as they are ...
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Auto-negotiation Expansion Register (ANER) - Register 6 Bit Bit Name 6.15-6.5 Reserved 6.4 PDF 6.3 LP_NP_ABLE 6.2 NP_ABLE 6.1 PAGE_RX 6.0 LP_AN_ABLE Control Register - Register 16 Bit Bit Name 16.15 IG_RMT_CMDS 16.14 AVG_PEAK_RL 16.13 EN_SHORT_CD 16.12 DIS_INC_NOISE 16.11 CMD_LO_PWR ...
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CMD_LO_SPD 16.8 CMD_HI_SPD 16.7 AID_ADR_NEG 16.6 CLR_NS_EVNT 16.5 SLC_LVL_ADP 16.4 PWR_DWN 16.3 Reserved 16.2 Speed 16.1 Power 16.0 Reserved Status Register - Register 17 Bit Bit Name 17.15 – Reserved 17.11 17.10 LINK_STA 17.9 DIS_LED_STR 17.8 Reserved 17.7 RX_RESERVED ...
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RX_PWR 17.5 RX_SPD 17.4 RX_VER 17.3 - Reserved 17.0 IMASK (Interrupt Mask) Register - Register 18 Bit Bit Name 18.15 – Software 18.10 Interrupts 18.9 MSK_RX_PCOM 18.8 MSK_TX_PCOM 18.7 – Reserved 18.4 18.3 MSK_PKT_RCV 18.2 MSK_PKT_XMIT 18.1 MSK_RMT_RCV 18.0 ...
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TX_PCOM_RDY 19.7 – Reserved 19.4 19.3 PKT_RCVD 19.2 PKT_XMITD 19.1 RMT_CMD_RCV 19.0 RMT_CMD_SNT TX_PCOM High Register - Register 20 Bit Bit Name 20.15 – TX_PCOM_HI 20.0 TX_PCOM Low Register - Register 21 Bit Bit Name 21.15 – TX_PCOM_LO 21.0 ...
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RX_PCOM Low Register - Register 23 Bit Bit Name 23.15 – RX_PCOM_LO 23.0 Peak Noise Register - Register 24 Bit Bit Name 24.15 - PEAK_LEVEL 24.8 24.7 - NOISE_LEVEL 24.0 Noise Control A Register - Register 25 Bit Bit Name ...
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DIS_LNK 27.0 FWENA Aid Address Register - Register 28 Bit Bit Name 28.15 - Reserved 28.8 28.7 - AID_ADDRESS 28.0 Aid Control Register - Register 29 Bit Bit Name 29.15 - AID_ISBI 29.8 29.7 - AID_INTERVAL 29.0 Symbol Control ...
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SPI Serial Management Register Map (INTFSEL = 1, GPSI Mode) Register Register Name Address 1-0 CNTRL 3-2 STATUS 5-4 IMASK 7-6 ISTAT 9-8 TX_PCOM_LO 11-10 TX_PCOM_HI 13-12 RX_PCOM_LO 15-14 RX_PCOM_HI 17-16 PEAK_NOISE 19-18 NOISE_CNTRL_A 21-20 NOISE_CNTRL_B 22 FWENA 25 AID_ADDRESS ...
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SPI Serial Management Control Register - Register 0 (continued) (INTFSEL = 1, GPSI Mode) Bit Bit Name 0.0 Reserved SPI Serial Management Control Register - Register 1 (INTFSEL = 1, GPSI Mode) Bit Bit Name 1.7 IG_RMT_CMDS 1.6 AVG_PEAK_RL 1.5 ...
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SPI Serial Management Status Register - Register 2 (continued) (INTFSEL = 1, GPSI Mode) Bit Bit Name 2.4 RX_VER 2.3 – 2.0 Reserved SPI Serial Management Status Register - Register 3 (INTFSEL = 1, GPSI Mode) Bit Bit Name 3.7 ...
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Software Interrupts 5.1 MSK_RX_PCOM 5.0 MSK_TX_PCOM ISTAT (Interrupt Status A) Register - Register 6 (INTFSEL = 1, GPSI Mode) This register reports the state of each interrupt source regardless of the state of the IMASK Register. Bit ...
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TX_PCOM Low B Register - Register 8 (INTFSEL = 1, GPSI Mode) Bit Bit Name 8.7 – 8.0 TX_PCOM_LOB TX_PCOM Low A Register - Register 9 (INTFSEL = 1, GPSI Mode) Bit Bit Name 9.7 – 9.0 TX_PCOM_LOA TX_PCOM High ...
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RX_PCOM Low A Register - Register 13 (INTFSEL = 1, GPSI Mode) Bit Bit Name 13.7 – RX_PCOM_LOA 13.0 RX_PCOM High B Register - Register 14 (INTFSEL = 1, GPSI Mode) Bit Bit Name 14.7 – RX_PCOM_HIB 14.0 RX_PCOM High ...
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Noise Floor Register - Register 18 (INTFSEL = 1, GPSI Mode) Bit Bit Name 18.7 - NSE_FLOOR 18.0 Noise Ceiling Register - Register 19 (INTFSEL = 1, GPSI Mode) Bit Bit Name 19.7 - NSE_CEILING 19.0 Noise Attack Register - ...
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Aid Interval Register - Register 26 (INTFSEL = 1, GPSI Mode) Bit Bit Name 26.7 - AID_INTERVAL 26.0 Aid Inter-Symbol Blanking Interval Register - Register 27 (INTFSEL = 1, GPSI Mode) Bit Bit Name 27.7 - AID_ISBI 27.0 ISBI Slow ...
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Mbps Home Phoneline Network PHY The integrated DM9801A transceiver is a physical layer device supporting home phoneline networking. It provides all of the PHY layer functions required to support 1 Mbps data transfers over existing residential phone wiring. All ...
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DM9801A Symbol Waveform All DM9801A symbols are composed at the transmitter of a silence interval and a pulse formed of an integer number of cycles (CYCLES_PER_PULSE frequency square wave (CENTER_FREQUENCY) that has been filtered with a bandpass filter. ...
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Home Phoneline Network Physical Layer Single Chip Transceiver AID Symbol Transmit Timing Figure 22 AID symbol Receive Timing Figure 23 DM9801A Final Version: DM9801A-DS-F01 May 30, 2001 ...
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Sync Transmit Timing The Sync interval (AID symbol 0) delineates the beginning of a frame and is composed of a SYNC_START pulse followed by a SYNC_END pulse after a fixed silence interval as shown in figure 22 above. Timing for ...
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Collisions (continued) In general, any received pulse at a station that does not conform to the pulse position requirements of AID symbols 0 through 7 shall indicate a collision on the wire. When a transmitting station senses a collision, it ...
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Data Receive Timing The incoming waveform is formed from the transmitted pulse along with any distortions and reflections that occur in the wiring network. The receiver detects the point at which the envelope of the received waveform crosses a set ...
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Data Symbol RLL25 Encoding The Run Length Limit (RLL25)code was developed for the Home Networking PHY. It produces highest bit rate for a given value of ISBI (Inter-Symbol Blanking Interval) and TIC size manor similar to run length ...
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Management Interfaces The DM9801A may be managed from either of two interfaces with managed parameters varying depending on the interface: 1. Remote control-word management commands embedded in the AID header on the wire network. 2. Management messages from the local ...
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Absolute Maximum Ratings* Symbol D ,A Supply Voltage VCC VCC V DC Input Voltage (VIN Output Voltage(VOUT) OUT T Ambient Temperature Range A Tc Case Temperature Range Tstg Storage Temperature Rang (Tstg) L Lead Temp. (TL, Soldering, ...
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AC Electrical Characteristics & Timing Waveforms otherwise) Analog Transmitter Timing Diagram Symbol Parameter Transmitter (Analog) t Pulse Width PW t Pulse Width High PWH t Pulse Width Low PWL t OSC Pulse Width High PWH t OSC Pulse Width Low ...
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MII-1M Nibble Transmit Timing Diagram TX_CLK TXD [0:3], TX_EN, TX_ER CRS HN+/- MII-1M Nibble Transmit Timing Parameters Symbol Parameter t TXD[0:3], TX_EN, TX_ER Setup TX_CLK High t TXD[0:3], TX_EN, TX_ER Hold TX h From ...
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MII-1M Receive Nibble Timing Parameters Symbol Parameter RXD[0:3), RX_DV, RX_ER Setup To RX_CLK High RXD[0:3], RX_DV, RX_ER Hold From RX_CLK High RXD[0:3] Out ( +/- Latency) t CRS ...
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GPSI-1M Transmit Timing Diagram STDCLK STXDAT STXEN CRS HN+/- GPSI-1M Transmit Timing Parameters Symbol Parameter t STXDATA STXEN, Setup STDCLK High t STXDAT, STXEN, Hold From TX h STDCLK High t STXEN Sampled To ...
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GPSI-1M Receive Timing Parameters Symbol Parameter SRXDAT Setup To SRDCLK High SRXDAT Hold From SRDCLK High SRXDAT Out ( +/- Latency) t CRS Asserted To SRXDAT 1 t ...
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SPI Master Mode Timing Diagram TWIDTHclk h SCLK TDLYscs l SCS# SO Instruction Byte SI SPI Master Timing Parameters Symbol Parameter TWIDTHclkh Positive half-cycle pulse width TWIDTHclkl Negative half-cycle pulse width TDLYscsl Falling clock edge to SCS# low TDLYsov Falling ...
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Magnetics Selection Guide The DM9801A requires an external bandpass filter to interface to the telephone line. Manufacturer PULSE DELTA Final Version: DM9801A-DS-F01 May 30, 2001 1M Home Phoneline Network Physical Layer Single Chip Transceiver Table 5 DM9801A Part Number B6003 ...
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Crystal Selection Guide A crystal can be used to generate Home Phoneline Network Physical Layer Single Chip Transceiver Figure 27 Crystal Circuit Diagram DM9801A 22P Cap 20MHz Crystal 22P Cap Version: DM9801A-DS-F01 May 30, 2001 Final ...
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Package Information LQFP 100L Outline Dimensions 75 76 100 1 e See Detail F Seating Plane Symbol Notes: 1. Dimension D & not include resin fins. 2. Dimension GD is for PC Board surface mount pad pitch design ...
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... Ordering Information Part Number Pin Count DM9801AE 100 Disclaimer The information appearing in this publication is believed to be accurate. Integrated circuits sold by DAVICOM Semiconductor are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. DAVICOM makes no warranty, express, statutory, implied or by description regarding the information in this ...