dm9000b Davicom Semiconductor, Inc., dm9000b Datasheet
dm9000b
Available stocks
Related parts for dm9000b
dm9000b Summary of contents
Page 1
... DAVICOM Semiconductor, Inc. With General Processor Interface Final Version: DM9000B-13-DS-F02 June 4, 2009 Ethernet Controller with General Processor Interface DM9000B Ethernet Controller DATA SHEET DM9000B Final Version: DM9000B-DS-F02 June 4, 2009 1 ...
Page 2
... Flow Control Threshold Register ( 09H ) .................................................................................................. 17 6.11 RX/TX Flow Control Register ( 0AH )........................................................................................................ 18 6.12 EEPROM & PHY Control Register ( 0BH ) ............................................................................................... 18 6.13 EEPROM & PHY Address Register ( 0CH ).............................................................................................. 18 6.14 EEPROM & PHY Data Register (EE_PHY_L:0DH Final Version: DM9000B-13-DS-F02 June 4, 2009 Ethernet Controller with General Processor Interface Content EE_PHY_H:0EH) ................................................. 18 DM9000B ...
Page 3
... Memory data write command with address increment Register (F8H)..................................................... 25 6.43 Memory data write address Register (FAH~FBH)..................................................................................... 25 6.44 TX Packet Length Register (FCH~FDH)................................................................................................... 25 6.45 Interrupt Status Register (FEH)................................................................................................................. 25 6.46 Interrupt Mask Register (FFH) .................................................................................................................. 25 7. EEPROM Format .............................................................................................................. 26 8. PHY Register Description ............................................................................................... 27 Final Version: DM9000B-13-DS-F02 June 4, 2009 Ethernet Controller with General Processor Interface DM9000B 3 ...
Page 4
... Adaptive Equalization .......................................................................................................................... 41 9.6.3 MLT-3 to NRZI Decoder ....................................................................................................................... 41 9.6.4 Clock Recovery Module....................................................................................................................... 41 9.6.5 NRZI to NRZ ........................................................................................................................................ 41 9.6.6 Serial to Parallel................................................................................................................................... 41 9.6.7 Descrambler......................................................................................................................................... 41 9.6.8 Code Group Alignment ........................................................................................................................ 42 9.6.9 4B5B Decoder...................................................................................................................................... 42 9.7 10Base-T Operation .................................................................................................................................... 42 9.8 Collision Detection ...................................................................................................................................... 42 9.9 Carrier Sense .............................................................................................................................................. 42 9.10 Auto-Negotiation........................................................................................................................................ 42 9.11 Power Reduced Mode............................................................................................................................... 43 Final Version: DM9000B-13-DS-F02 June 4, 2009 Ethernet Controller with General Processor Interface DM9000B 4 ...
Page 5
... Non Auto MDIX Transformer Application ) ........................................................ 50 11.4 Power Decoupling Capacitors ................................................................................................................... 51 11.5 Ground Plane Layout ................................................................................................................................ 52 11.6 Power Plane Partitioning ........................................................................................................................... 53 11.7 Magnetic Selection Guide ......................................................................................................................... 54 11.8 Crystal Selection Guide ............................................................................................................................. 54 12. Package Information ..................................................................................................... 55 13. Ordering Information..................................................................................................... 56 Final Version: DM9000B-13-DS-F02 June 4, 2009 Ethernet Controller with General Processor Interface ° ......................................................................................................... 44 DM9000B 5 ...
Page 6
... Final Version: DM9000B-13-DS-F02 June 4, 2009 Ethernet Controller with General Processor Interface processors. The PHY of the DM9000B can interface to the UTP3 10Base-T and UTP5 in 100Base-TX with HP Auto-MDIX fully compliant with the IEEE 802.3u Spec. Its auto-negotiation function will automatically configure the DM9000B to take the maximum advantage of its abilities ...
Page 7
... Support 100M Fiber interface. ■ Integrated 16K Byte SRAM ■ Build in 3.3V to 1.8V regulator ■ Supports early Transmit Final Version: DM9000B-13-DS-F02 June 4, 2009 Ethernet Controller with General Processor Interface ■ Supports IP/TCP/UDP checksum generation and checking ■ Supports automatically load vendor ID and product ID from EEPROM ■ ...
Page 8
... Pin Configuration 4.1 (16-bit mode) CS# LED2 LED1 PWRST# TEST VDD X2 X1 GND SD RXGND BGGND Final Version: DM9000B-13-DS-F02 June 4, 2009 Ethernet Controller with General Processor Interface DM9000B 42 (16-bit mode DM9000B 24 SD14 VDD 23 22 SD15 21 EECS 20 EECK EEDIO ...
Page 9
... CS# LED2 LED1 PWRST# TEST VDD X2 X1 GND SD RXGND BGGND Final Version: DM9000B-13-DS-F02 June 4, 2009 Ethernet Controller with General Processor Interface DM9000B 42 (8-bit mode DM9000B 24 LED3 VDD 23 22 WAKE 21 EECS 20 EECK EEDIO 19 SD0 18 SD1 ...
Page 10
... This pin is low active at default, its polarity can be modified by EEPROM setting. See the EEPROM content description for detail Chip Select A default low active signal used to select the DM9000B. Its polarity can be I,PD modified by EEPROM setting. See the EEPROM content description for detail. ...
Page 11
... BGGND 1 BGRES 2 RXVDD18 9 TXVDD18 Final Version: DM9000B-13-DS-F02 June 4, 2009 Ethernet Controller with General Processor Interface General I/O Ports I/O Registers GPCR and GPR can program these pins These pins are input ports at default. Type Clock to EEPROM This pin is also used as the strap pin of the polarity of the INT pin When this pin is pulled high, the INT pin is low active ...
Page 12
... These two pins are the transmit output in MDI mode or the receive input in MDIX mode. Type Operation Mode I Force to ground in normal application Power on Reset I Active low signal to initiate the DM9000B The DM9000B is ready after 5us when this pin deasserted Type Digital VDD P 3.3V power input Digital GND P DM9000B Description ...
Page 13
... Vendor Control and Status Register Set The DM9000B implements several control and status registers, which can be accessed by the host. These CSRs Register NCR Network Control Register NSR Network Status Register TCR TX Control Register TSR I TX Status Register I TSR II TX Status Register II ...
Page 14
... FDX PS0,RO PS00, 2:1 LBK RW 0 RST P0,RW Final Version: DM9000B-13-DS-F02 June 4, 2009 Ethernet Controller with General Processor Interface T = default value from strap pin <Access Type> Read only RW = Read/Write R/C = Read and Clear RW/C1=Read/Write and Cleared by write Write only Reserved bits are shaded and should be written with 0. ...
Page 15
... EC PS0,RO 1:0 RESERVED 0,RO Final Version: DM9000B-13-DS-F02 June 4, 2009 Ethernet Controller with General Processor Interface Media Speed 0:100Mbps 1:10Mbps, when Internal PHY is used. This bit has no meaning when LINKST=0 Link Status 0:link failed 1:link OK, Wakeup Event Status. Clears by read or write 1 (work in 8-bit mode) ...
Page 16
... CE PS0,RO 0 FOE PS0,RO Final Version: DM9000B-13-DS-F02 June 4, 2009 Ethernet Controller with General Processor Interface Transmit Jabber Time Out It is set to indicate that the transmitted frame is truncated due to more than 2048 bytes are transmitted Loss of Carrier It is set to indicate the loss of carrier during the frame transmission not valid in ...
Page 17
... HWOT PS3, RW 3:0 LWOT PS8, RW Final Version: DM9000B-13-DS-F02 June 4, 2009 Ethernet Controller with General Processor Interface Receive Overflow Counter Overflow This bit is set when the ROC has an overflow condition Receive Overflow Counter This is a statistic counter to indicate the received packet count upon FIFO overflow Back Pressure High Water Overflow Threshold ...
Page 18
... DA matches and RX SRAM is over BPHW of register 8. RX Pause Packet Status, latch and read clearly RX Pause Packet Current Status Flow Control Enable Set to enable the flow control mode (i.e. can disable DM9000B TX function) Reserved Reload EEPROM. Driver needs to clear it up after the operation completes Write EEPROM Enable EEPROM or PHY Operation Select When reset, select EEPROM ...
Page 19
... GPC31 000,RW 0 RESERVED P1,RO Final Version: DM9000B-13-DS-F02 June 4, 2009 Ethernet Controller with General Processor Interface Reserved When set, it enables Link Status Change Wake up Event This bit will not be affected after software reset When set, it enables Sample Frame Wake up Event This bit will not be affected after software reset ...
Page 20
... Bit Name Default 7 LED P0,RW Final Version: DM9000B-13-DS-F02 June 4, 2009 Ethernet Controller with General Processor Interface Reserved General Purpose Output 6~4 (in 8-bit mode) These bits are reflect to pin GP6~4 respectively. General Purpose (in 8-bit mode) When the correspondent bit of General Purpose Control Register is 1, the value of the bit is reflected to pin GP3~1 respectively ...
Page 21
... P0,RW 1 FB1 P0,RW 0 FB0 P0,RW Final Version: DM9000B-13-DS-F02 June 4, 2009 Ethernet Controller with General Processor Interface Retry Late Collision Packet Re-transmit the packet with late-collision Disable TX Under run Retry Disable to re-transmit the underruned packet One Packet Mode When set, only one packet transmit command can be issued before transmit completed ...
Page 22
... IPP PS0,RO 1 RCSEN PS0,RW 0 DCSE PS0,RW Final Version: DM9000B-13-DS-F02 June 4, 2009 Ethernet Controller with General Processor Interface Description Early Transmit Enable Enable bits[2:0] Early Transmit Status II Early Transmit Status I Reserved Early Transmit Threshold Start transmit when data write to TX FIFO reach the byte-count threshold ...
Page 23
... IOW_SPIKE P0,RW 0 IOR_SPIKE P1,RW Final Version: DM9000B-13-DS-F02 June 4, 2009 Ethernet Controller with General Processor Interface External PHY Address Enabled When register 34H bit 0 is set to ‘1’, the PHY address field in MII Management Interface format is defined at bit 4~0. External PHY Address Bit 4~0 The PHY address field in MII Management Interface format. ...
Page 24
... ON Read data from RX SRAM. After the read of this command, the read pointer of internal SRAM is unchanged. And the DM9000B starts to pre-fetch the SRAM data to internal data buffers. Read data from RX SRAM. After the read of this command, the read pointer of internal SRAM is unchanged Read data from RX SRAM ...
Page 25
... PTI PS0,RW 0 PRI PS0,RW Final Version: DM9000B-13-DS-F02 June 4, 2009 Ethernet Controller with General Processor Interface Write Data to TX SRAM After the write of this command, the write pointer is increased depends on the operator mode. (8-bit or 16-bit respectively) Memory Data Write_ address High Byte ...
Page 26
... Vendor ID 4 Product ID 5 Pin control 6 Wake-up mode control 7 Final Version: DM9000B-13-DS-F02 June 4, 2009 Ethernet Controller with General Processor Interface offset 0~5 6 Byte Ethernet Address Bit 1:0=01: Update vendor ID and product ID Bit 3:2=01: Accept setting of WORD6 [8:0] Bit 5:4=01: reserved Bit 7:6=01: Accept setting of WORD7 [3:0] (in 8-bit mode) ...
Page 27
... Value>, <Access Type> / <Attribute(s)> Where： <Reset Value>: 1 Bit set to logic one 0 Bit set to logic zero X No default value Final Version: DM9000B-13-DS-F02 June 4, 2009 Ethernet Controller with General Processor Interface Power Isolate Restart Full Coll ...
Page 28
... When auto-negotiation is disabled (bit 12 of this register cleared), this bit has no function and it should be cleared. This bit is self-clearing and it will keep returning to a value of 1 until auto-negotiation is initiated by the DM9000B. The operation of the auto-negotiation process will not be affected by the management entity that clears this bit ...
Page 29
... DM9000B is not able to perform 100BASE-TX in half duplex mode 1,RO/P 10BASE-T Full Duplex Capable 1 = DM9000B is able to perform 10BASE-T in full duplex mode 0 = DM9000B is not able to perform 10BASE-TX in full duplex mode 1,RO/P 10BASE-T Half Duplex Capable 1 = DM9000B is able to perform 10BASE-T in half duplex mode 0 = DM9000B is not able to perform 10BASE-T in half duplex mode ...
Page 30
... Extended capability 8.3 PHY ID Identifier Register #1 (PHYID1 The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM9000B. The Identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), a vendor's model number, and a model revision number. DAVICOM Semiconductor's IEEE assigned OUI is 00606E. ...
Page 31
... Auto-negotiation Advertisement Register (ANAR This register contains the advertised abilities of this DM9000B device as they will be transmitted to its link partner during Auto-negotiation. Bit Bit Name 4.15 NP 4.14 ACK 4.13 RF 4.12 Reserved -4.11 4.10 FCS 4.9 T4 4.8 TX_FDX 4.7 TX_HDX 4.6 10_FDX 4.5 10_HDX 4.4-4.0 Selector <00001>, RW Protocol Selection Bits Final Version: DM9000B-13-DS-F02 June 4, 2009 ...
Page 32
... Link partner, no next page available 0, RO Acknowledge 1 = Link partner ability data reception acknowledged 0 = Not acknowledged The DM9000B's auto-negotiation state machine will automatically control this bit from the incoming FLP bursts. Software should not attempt to write to this bit 0, RO Remote Fault 1 = Remote fault indicated by link partner ...
Page 33
... Local Device Next Page Able NP_ABLE = 1: DM9000B, next page available NP_ABLE = 0: DM9000B, no next page DM9000B does not support this function, so this bit is always 0 0, RO/LH New Page Received A new link code word page received. This bit will be automatically cleared when the register (register 6) is read by management ...
Page 34
... RO 17.12 10HDX 1, RO 17.11 Reserved 0, RO Final Version: DM9000B-13-DS-F02 June 4, 2009 Ethernet Controller with General Processor Interface Reset State Machine 0, RW When writes 1 to this bit, all state machines of PHY will be reset. This bit is self-clear after reset is completed MF Preamble Suppression Control ...
Page 35
... This bit is valid only in 10Mbps operation Heartbeat Enable 1 = Heartbeat function enabled 0 = Heartbeat function disabled When the DM9000B is configured for full duplex operation, this bit will be ignored (the collision/heartbeat function is invalid in full duplex mode), This bit is valid only in 10Mbps operation. Squelch Enable ...
Page 36
... MDIX_CNTL MDI/MDIX,RO The polarity of MDI/MDIX value 20.6 AutoNeg_lpbk 20.5 Mdix_fix Value Final Version: DM9000B-13-DS-F02 June 4, 2009 Ethernet Controller with General Processor Interface Reserved Read as 0, ignore on write Vendor power down control test Vendor power down control test Vendor power down control test ...
Page 37
... Power Saving Control Register (PSCR) – 29 Bit Bit Name 29.15-12 RESERVED 29.11 PREAMBLEX 29.10 AMPLITUDE 29.9 TX_PWR 29.8-0 RESERVED Final Version: DM9000B-13-DS-F02 June 4, 2009 Ethernet Controller with General Processor Interface 0,RW HP Auto-MDIX Down Manual force MDI/MDIX. 1: Disable HP Auto-MDIX , MDIX_CNTL value depend on 20.5 0: Enable HP Auto-MDIX 0,RW Vendor monitor select 0,RW Vendor monitor select 0,RW Reserved Force application ...
Page 38
... Functional Description 9.1 Host Interface The host interface is a general processor local bus that using chip select (pin CS#) to access DM9000B. Pin CS# is default low active which can be re-defined by EEPROM setting. There are only two addressing ports through the access of the host interface. One port is the INDEX port and the other is the DATA port ...
Page 39
... IDLEs into the transmit data stream until Transmit Enable is asserted and the next transmit packet is detected. The DM9000B includes a Bypass 4B5B conversion option within the 100Base-TX Transmitter for support of applications like 100 Mbps repeaters which do not Require 4B5B conversion. ...
Page 40
... Final Version: DM9000B-13-DS-F02 June 4, 2009 Ethernet Controller with General Processor Interface Meaning 4B code 3210 Data 0 0000 Data 1 0001 Data 2 0010 Data 3 0011 Data 4 0100 Data 5 0101 Data 6 0110 Data 7 0111 ...
Page 41
... Version: DM9000B-13-DS-F02 June 4, 2009 Ethernet Controller with General Processor Interface 9.6.3 MLT-3 to NRZI Decoder The DM9000B decodes the MLT-3 information from the Digital Adaptive Equalizer into NRZI data. 9.6.4 Clock Recovery Module The Clock Recovery Module accepts NRZI data from the MLT-3 to NRZI decoder. The Clock Recovery Module locks onto the data stream and extracts the 125 MHz reference clock ...
Page 42
... The T/R symbol pair is also stripped from the nibble, presented to the Reconciliation layer. 9.7 10Base-T Operation The 10Base-T transceiver is IEEE 802.3u compliant. When the DM9000B is operating in 10Base-T mode, the coding scheme is Manchester. Data processed for transmit is presented in nibble format, converted to a serial bit stream, then the Manchester encoded. ...
Page 43
... Power Reduced Mode The Signal detect circuit is always turned to monitor whether there is any signal on the media (cable disconnected). The DM9000B automatically turns off the power and enters the Power Reduced mode, whether its operation mode is N-way or force mode. When enters the Power Reduced mode, the transmit circuit still sends out fast link pules with minimum power consumption ...
Page 44
... V 100TX+/- Differential Output TD100 Voltage V 10TX+/- Differential Output Voltage TD10 I 100TX+/- Differential Output TD100 Current I 10TX+/- Differential Output Current TD10 Final Version: DM9000B-13-DS-F02 June 4, 2009 Ethernet Controller with General Processor Interface Parameter Min. -0.3 -0.5 -0.3 -65 0 － Min. 3.135 --- --- --- ...
Page 45
... T4 PWRST# high to EECS burst end Note: The DM9000B needs the time about 3ms to down load the setting from EEPROM after PWRST# deasserted, During the period, the CS# pin is not recognized even no EEPROM present. So, please note that processor only access DM9000B after PWRST# deasserted 3ms. ...
Page 46
... T IOR# invalid to next IOR#/IOW# valid 6 When read DM9000B register T2+T IOR# valid to next IOR#/IOW# valid 6 When read DM9000B memory with F0h register T +T IOR# valid to next IOR#/IOW# valid 2 6 When read DM9000B memory with F2h register *Note： ...
Page 47
... T IOW# Invalid to next IOW#/IOR# valid 6 When write DM9000B INDEX port T IOW# Invalid to next IOW#/IOR# valid 6 When write DM9000B DATA port T +T IOW# valid to next IOW#/IOR# valid 2 6 When write DM9000B memory Note：(The default clk period is 20ns) ...
Page 48
... T EEDIO Setup Time when output 4 T5 EEDIO Hold Time when output T EEDIO Setup Time when input 6 T EEDIO Hold Time when input 7 Final Version: DM9000B-13-DS-F02 June 4, 2009 Ethernet Controller with General Processor Interface Parameter DM9000B Min. Typ. ...
Page 49
... Place the transformer as close as possible to the RJ-45 connector. Place all the 50Ω resistors as close as possible to the DM9000B RXI± and TXO± pins. Traces routed from RXI± and TXO± to the transformer should run in close pairs directly to the transformer. The designer should be careful not to cross the transmit and receive pairs ...
Page 50
... Non Auto MDIX Transformer Application ) Final Version: DM9000B-13-DS-F02 June 4, 2009 Ethernet Controller with General Processor Interface Figure 11-2 Non Auto MDIX Transformer Application DM9000B 50 ...
Page 51
... Power Decoupling Capacitors Davicom Semiconductor recommends placing all the decoupling capacitors for all power supply pins as close as possible to the power pads of the DM9000B (The best placed distance is < 3mm from pin). The recommended decoupling capacitor is 0.1μF or 0.01μF, as required by the design layout. ...
Page 52
... EMI. Ground plane partitioning can cause increased EMI emissions that could make the network interface card not comply with specific FCC Final Version: DM9000B-13-DS-F02 June 4, 2009 Ethernet Controller with General Processor Interface regulations (part 15). Figure 11-4 shows a recommended ground layout scheme ...
Page 53
... Power Plane Partitioning The power planes should be approximately illustrated in Figure 11-5. Final Version: DM9000B-13-DS-F02 June 4, 2009 Ethernet Controller with General Processor Interface Figure 11-5 Power Plane Partitioning DM9000B 53 ...
Page 54
... A crystal can be used to generate the 25MHz reference clock instead of an oscillator. The crystal must be a fundamental type, and series-resonant. Final Version: DM9000B-13-DS-F02 June 4, 2009 Ethernet Controller with General Processor Interface pin-to-pin equivalents. Designers should test and qualify all magnetic specifications before using them in an application ...
Page 55
... D 0.354BSC D1 0.276BSC E 0.354BSC E1 0.276BSC 0.020BSC L 0.018 0.024 0.030 L1 0.039REF y 0.003MAX Final Version: DM9000B-13-DS-F02 June 4, 2009 Ethernet Controller with General Processor Interface Notes: Dimensions determined at seating plane. Min. Nom. Max 1.60 2. Dimensions D1 and E 1do not include mold 0.05 - 0.15 protrusion. D1 and E1 are maximum plastic body 1 ...
Page 56
... Conditions beyond those listed for the absolute maximum may destroy or damage the products. In addition, conditions for sustained periods at near the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and function. Final Version: DM9000B-13-DS-F02 June 4, 2009 Ethernet Controller with General Processor Interface application circuits illustrated in this document are for reference purposes only ...