dm9302 Davicom Semiconductor, Inc., dm9302 Datasheet
dm9302
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dm9302 Summary of contents
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... DAVICOM Semiconductor, Inc. 10/100Mbps Ethernet Fiber/Twisted Pair Media Converter with Local bus DM9302 DATA SHEET Preliminary Version: DM9302-DS-P01 July 30, 2009 ...
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... Strap pins table.............................................................................................................................................. 14 6. CONTROL AND STATUS REGISTER SET................................................................... 15 6.1 Network Control Register (00H) ................................................................................................................... 17 6.2 Network Status Register (01H)..................................................................................................................... 17 6.3 TX Control Register (02H)............................................................................................................................. 18 6.4 RX Control Register (05H) ............................................................................................................................ 18 2 10/100Mbps Ethernet Fiber/Twisted Pair Media Converter with Local bus CONTENT DM9302 Preliminary datasheet DM9302-15-DS-P01 July 30, 2009 ...
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... Transmit Check Sum Control Register (31H) ........................................................................................... 20 6.21 Receive Check Sum Control Status Register (32H)................................................................................. 21 6.22 uP Data Bus driving capability Register (38H) ......................................................................................... 21 6.23 IRQ Pin Control Register (39H) .................................................................................................................. 21 6.24 TX/RX Memory Size Control Register (3FH) ............................................................................................. 22 Preliminary datasheet DM9302-15-DS-P01 July 30, 2009 10/100Mbps Ethernet Fiber/Twisted Pair Media Converter with Local bus DM9302 3 ...
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... MIB Counter Port Index Register (80H) ..................................................................................................... 28 6.42 MIB Counter Data Registers (81H~84H) .................................................................................................... 28 6.43 Port-Based VLAN Mapping Table Registers (B0H~BFH)......................................................................... 29 6.44 TOS Priority Map Registers (C0H~CFH).................................................................................................... 29 6.45 VLAN Priority Map Registers (D0H~D1H) ................................................................................................. 32 4 10/100Mbps Ethernet Fiber/Twisted Pair Media Converter with Local bus DM9302 Preliminary datasheet DM9302-15-DS-P01 July 30, 2009 ...
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... PHY ID Identifier Register #2 (PHYID2) – 03H............................................................................................. 40 8.5 Auto-negotiation Advertisement Register (ANAR) – 04H.......................................................................... 40 8.6 Auto-negotiation Link Partner Ability Register (ANLPAR) – 05H ............................................................. 41 8.7 Auto-negotiation Expansion Register (ANER) - 06H ................................................................................. 42 Preliminary datasheet DM9302-15-DS-P01 July 30, 2009 10/100Mbps Ethernet Fiber/Twisted Pair Media Converter with Local bus DM9302 5 ...
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... Inter-Packet Gap (IPG) ............................................................................................................................ 49 9.2.5 Back-off Algorithm.................................................................................................................................... 49 9.2.6 Late Collision............................................................................................................................................ 49 9.2.7 Half Duplex Flow Control ......................................................................................................................... 49 9.2.8 Full Duplex Flow Control .......................................................................................................................... 49 9.2.9 Partition Mode .......................................................................................................................................... 49 9.2.10 Broadcast Storm Filtering....................................................................................................................... 50 9.2.11 Bandwidth Control.................................................................................................................................. 50 9.2.12 Port Monitoring Support ......................................................................................................................... 50 6 10/100Mbps Ethernet Fiber/Twisted Pair Media Converter with Local bus DM9302 Preliminary datasheet DM9302-15-DS-P01 July 30, 2009 ...
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... MLT-3 to NRZI Decoder........................................................................................................................ 55 9.3.2.4 Clock Recovery Module ........................................................................................................................ 55 9.3.2.5 NRZI to NRZ ......................................................................................................................................... 55 9.3.2.6 Serial to Parallel .................................................................................................................................... 55 9.3.2.7 Descrambler .......................................................................................................................................... 55 9.3.2.8 Code Group Alignment.......................................................................................................................... 56 9.3.2.9 4B5B Decoder....................................................................................................................................... 56 9.3.3 10Base-T Operation................................................................................................................................. 56 9.3.4 Collision Detection ................................................................................................................................... 56 9.3.5 Carrier Sense ........................................................................................................................................... 56 9.3.6 Auto-Negotiation ...................................................................................................................................... 56 10. DC AND AC ELECTRICAL CHARACTERISTICS ..................................................... 57 Preliminary datasheet DM9302-15-DS-P01 July 30, 2009 10/100Mbps Ethernet Fiber/Twisted Pair Media Converter with Local bus DM9302 7 ...
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... Operating Conditions.................................................................................................................................. 57 10.3 DC Electrical Characteristics ..................................................................................................................... 58 10.4 AC characteristics ....................................................................................................................................... 59 10.4.1 Power On Reset Timing ......................................................................................................................... 59 10.4.2 Processor I/O Read Timing.................................................................................................................... 60 10.4.3 Processor I/O Write Timing .................................................................................................................... 61 10.4.4 EEPROM timing ..................................................................................................................................... 62 11. PACKAGE INFORMATION........................................................................................ 63 12. ORDERING INFORMATION ...................................................................................... 64 8 10/100Mbps Ethernet Fiber/Twisted Pair Media Converter with Local bus DM9302 Preliminary datasheet DM9302-15-DS-P01 July 30, 2009 ...
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... GENERAL DESCRIPTION The DM9302 Fiber converter is complied with IEEE802.3 standards, and designed to convert data signal between 10/100 Base-TX and 100 Base-FX fast Ethernet. 2. BLOCK DIAGRAM Port 0 100M PECL TXMT/ PECL RXCR TX/RX Port 1 10/ 100 M PHY MDI / MDIX bit Processor Processor ...
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... Local bus slave architecture TCP/IP/UDP/IPv4 checksum offload Compatible with 3.3V and 5.0V tolerant I/O DSP PHY with HP Auto-MDIX, DSP architecture PHY Transceiver 64-pin LQFP, 0.18 um process, support Lead-Free and Halogen–Free 10 10/100Mbps Ethernet Fiber/Twisted Pair Media Converter with Local bus DM9302 Preliminary datasheet DM9302-15-DS-P01 July 30, 2009 ...
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... SPD1_LED LNK0_LED 57 SPD0_LED 58 59 TEST2 60 CMD 61 VCCI CS IOW# 64 GND Preliminary datasheet DM9302-15-DS-P01 July 30, 2009 10/100Mbps Ethernet Fiber/Twisted Pair Media Converter with Local bus DM9302 DM9302 TEST1 32 GND 31 30 PWRST# 29 EECS EECK 28 EEDIO 27 VCC3 26 SD15 25 SD14 24 23 GND SD13 22 SD12 ...
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... Default is low active. Its polarity can be changed by EEPROM setting. Pin Name I/O EEDIO I,/O EEPROM Data In/Out EECK O,PD EEPROM Serial Clock This pin is used as the clock for the EEPROM data transfer. EECS O,PD EEPROM Chip Selection. DM9302 Description Description Preliminary datasheet DM9302-15-DS-P01 July 30, 2009 ...
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... Fiber transmitter data pair. RX0+/- I/O Port Fiber receiver data pair. BGRES I/O Band gap Pin Connect a 1.4Kohm ±1% resistor to Analog Ground (AGND) in application Fiber Signal Detect VCNTL I/O 1.8V Voltage control VREF O Voltage Reference Connect a 0.1uF capacitor to ground in application. DM9302 Description Description Description 13 ...
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... Low active with minimum 1ms TEST1 I,PD Tie to ground in application TEST2 I,PD Tie to ground in application Pin Name I/O VCC3 P Digital 3.3V VCCI P Internal 1.8V core power GND P Digital GND AVDD3 P Analog 3.3V power AVDDI P Analog 1.8V power AGND P Analog GND Description DM9302 Description Description Preliminary datasheet DM9302-15-DS-P01 July 30, 2009 ...
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... CONTROL AND STATUS REGISTER SET The DM9302 implements several control and status registers (CSR), which can be accessed by the host. Register NCR Network Control Register NSR Network Status Register TCR TX Control Register RCR RX Control Register RSR RX Status Register ROCR Receive Overflow Counter Register ...
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... B0-BFH 0FH C0-CFH 00H~FFH D0-D1H 50H,FAH F0H XXH F2H XXH F4H 00H F5H 00H F6H XXH F8H XXH FAH 00H FBH 00H FCH XXH FDH XXH FEH 00H FFH 00H Preliminary datasheet DM9302-15-DS-P01 July 30, 2009 ...
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... If bit 5 of NCR is set, this bit is cleared by write 1; Otherwise it can be cleared by read or write 1. TX Packet 1 Complete status. This bit is set after transmit completion of packet index 1 If bit 5 of NCR is set, this bit is cleared by write 1; Otherwise it can be cleared by read or write 1. Reserved DM9302 Description Description 17 ...
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... Reserved RX Flow Control Enable Enables the pause packet for high/low water threshold control Reserved Reserved Reload EEPROM. Driver needs to clear it up after the operation completes Write EEPROM Enable DM9302 Description Description Description Description Description Description Preliminary datasheet DM9302-15-DS-P01 July 30, 2009 ...
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... Physical Address Byte 5 (15H) Physical Address Byte 4 (14H) Physical Address Byte 3 (13H) Physical Address Byte 2 (12H) Physical Address Byte 1 (11H) Physical Address Byte 0 (10H) Multicast Address Byte 7 (1DH) Multicast Address Byte 6 (1CH) Multicast Address Byte 5 (1BH) DM9302 Description Description Description Description Description 19 ...
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... Exceed buffer RX pointer restriction disable Reserved Vendor ID High Byte (29H) Vendor ID Low Byte (28H) CHIP Revision Reserved UDP Checksum Generation Enable TCP Checksum Generation Enable IP Checksum Generation Enable DM9302 Description Description Description Description Description Description Description Preliminary datasheet DM9302-15-DS-P01 July 30, 2009 ...
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... Eliminate IOW spike 1: eliminate about 2ns IOW spike Eliminate IOR spike 1: eliminate about 2ns IOR spike Reserved IRQ Pin Output Type Control 1: IRQ Open-Collector output 0: IRQ direct output IRQ Pin Polarity Control 1: IRQ active low 0: IRQ active high DM9302 Description Description Description 21 ...
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... VLAN tag defined in Reg. 6EH and 6FH. Replace priority field in the tag with value define in Reg 6FH bit 7~5. VLAN mode enable 1: 802.1Q base VLAN mode enable 0: port-base VLAN only DM9302 Description Description Description Preliminary datasheet DM9302-15-DS-P01 July 30, 2009 ...
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... Control with Ingress or Egress, ref to Register 67H Broadcast packet filter 0: accept broadcast packets 1: reject broadcast packets Multicast packet filter 0: accept multicast packets 1: reject multicast packets Broadcast Storm Control 0: only broadcast packets storm are controlled 1: multicast packets also same as broadcast storm control. DM9302 Description Description Description Description 23 ...
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... Reserved Packet Transmit Disabled All packets can not be forward to this port. Packet receive Disabled All received packets are discarded. Address Learning Disabled The Source Address (SA) field of packet is not learned to address table. DM9302 Description Description Preliminary datasheet DM9302-15-DS-P01 July 30, 2009 ...
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... Egress Rate table below 0000: none 0001: 64Kbps 0010: 128Kbps 0011: 256Kbps 0100: 512Kbps 0101: 1Mbps 0110: 2Mbps 0111: 4Mbps 1000: 8Mbps 1001: 16Mbps 1010: 32Mbps 1011: 48Mbps 1100: 64Mbps 1101: 72Mbps 1110: 80Mbps 1111: 88Mbps DM9302 Description 25 ...
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... Bandwidth table below 0000: none 0001: 64Kbps 0010: 128Kbps 0011: 256Kbps 0100: 512Kbps 0101: 1Mbps 0110: 2Mbps 0111: 4Mbps 1000: 8Mbps 1001: 16Mbps 1010: 32Mbps 1011: 48Mbps 1100: 64Mbps 1101: 72Mbps 1110: 80Mbps 1111: 88Mbps DM9302 Description Preliminary datasheet DM9302-15-DS-P01 July 30, 2009 ...
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... packet with VLAN tag, the priority of this packet is decode from ToS field. ToS Priority Classification Disable The priority information from ToS field of IP packet is ignored. 802.1 p Priority Classification Disable The priority information from VLAN tag field is ignored. DM9302 Description Description Description Description Description ...
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... Write the MIB counter index to this register before read them. MIB counter Data Register bit 0~7 MIB counter Data Register bit 8~15 MIB counter Data Register bit 16~23 MIB counter Data Register bit 24~31 DM9302 Description Description Description Description Preliminary datasheet DM9302-15-DS-P01 July 30, 2009 ...
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... If Reg.53H. bit 7=1 :TOS[7:2]=04H, otherwise TOS]7:5]=04H If Reg.53H. bit 7=1 :TOS[7:2]=0BH If Reg.53H. bit 7=1 :TOS[7:2]=0AH If Reg.53H. bit 7=1 :TOS[7:2]=09H If Reg.53H. bit 7=1 :TOS[7:2]=08H If Reg.53H. bit 7=1 :TOS[7:2]=0FH If Reg.53H. bit 7=1 :TOS[7:2]=0EH If Reg.53H. bit 7=1 :TOS[7:2]=0DH If Reg.53H. bit 7=1 :TOS[7:2]=0CH DM9302 Description Description Description Description Description 29 ...
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... If Reg.53H. bit 7=1 :TOS[7:2]=22H If Reg.53H. bit 7=1 :TOS[7:2]=21H If Reg.53H. bit 7=1 :TOS[7:2]=20H If Reg.53H. bit 7=1 :TOS[7:2]=27H If Reg.53H. bit 7=1 :TOS[7:2]=26H If Reg.53H. bit 7=1 :TOS[7:2]=25H If Reg.53H. bit 7=1 :TOS[7:2]=24H DM9302 Description Description Description Description Description Description Preliminary datasheet DM9302-15-DS-P01 July 30, 2009 ...
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... If Reg.53H. bit 7=1 :TOS[7:2]=34H If Reg.53H. bit 7=1 :TOS[7:2]=3BH If Reg.53H. bit 7=1 :TOS[7:2]=3AH If Reg.53H. bit 7=1 :TOS[7:2]=39H If Reg.53H. bit 7=1 :TOS[7:2]=38H If Reg.53H. bit 7=1 :TOS[7:2]=3FH If Reg.53H. bit 7=1 :TOS[7:2]=3EH If Reg.53H. bit 7=1 :TOS[7:2]=3DH If Reg.53H. bit 7 =1 :TOS[7:2]=3CH DM9302 Description Description Description Description Description Description 31 ...
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... VLAN priority tag value = 04H Read data from RX SRAM. After the read of this command, the read pointer of internal SRAM is unchanged. And the DM9302 starts to pre-fetch the SRAM data to internal data buffers. Read data from RX SRAM. After the read of this command, the read pointer is ...
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... When register FFH bit 7 is “0”, register FBH and FAH can be used as memory byte address to write internal 64K-byte memory. When register FFH bit 7 is “1”, register FBH and FAH are reserved. The processor port transmit memory address is generated by DM9302 automatically. Bit Name ...
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... When word 16 bit 3:2 is “01”, after power on reset: This word bit 7~0 will be loaded to port 1 Reg. 61H bit 7~0 This word bit 15~8 will be loaded to port 1 Reg. 66H bit 7~0 When word 16 bit 3:2 is “01”, after power on reset: Description DM9302 Preliminary datasheet DM9302-15-DS-P01 July 30, 2009 ...
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... This word bit 7~0 will be loaded to Reg. BEH bit 7~0 This word bit 15~8 will be loaded to Reg. BFH bit 7~0 When word 16 bit 11:10 is “01”, after power on reset: This word bit 7~0 will be loaded to Reg. C0H bit 7~0 This word bit 15~8 will be loaded to Reg. C1H bit 7~0 DM9302 35 ...
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... This word bit 15~8 will be loaded to Reg. CDH bit 7~0 When word 16 bit 11:10 is “01”, after power on reset: This word bit 7~0 will be loaded to Reg. CEH bit 7~0 This word bit 15~8 will be loaded to Reg. CFH bit 7~0 Set application DM9302 Preliminary datasheet DM9302-15-DS-P01 July 30, 2009 ...
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... Reset Pream. LED R-EN St. Mch Supr. PHY ADDR [4:0] Auto-N. Monitor Bit [3:0] Reserved AutoNe Mdix_fix Mdix_d MonSel MonSel g_dlpbk Value own 1 Disconnect_counter Reversed RW = Read/Write DM9302 1 0 Jabber Extd Detect Cap 0000 New Pg LP Rcv AutoN Cap. Sleep Remote mode LoopOut Polarity ...
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... When auto-negotiation is disabled (bit 12 of this register cleared), this bit has no function and it should be cleared. This bit is self-clearing and it will keep returning to a value of 1 until auto-negotiation is initiated by the DM9302. The operation of the auto-negotiation process will not be affected by the management entity that clears this bit ...
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... DM9302 is not able to perform in 100BASE-T4 mode 1,RO/P 100BASE-TX Full Duplex Capable 1 = DM9302 is able to perform 100BASE-TX in full duplex mode 0 = DM9302 is not able to perform 100BASE-TX in full duplex mode 1,RO/P 100BASE-TX Half Duplex Capable 1 = DM9302 is able to perform 100BASE-TX in half duplex mode 0 = DM9302 is not able to perform 100BASE-TX in half duplex ...
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... PHY ID Identifier Register #1 (PHYID1) – 02H The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM9302. The Identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), a vendor's model number, and a model revision number. DAVICOM Semiconductor's IEEE assigned OUI is 00606E. ...
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... Controller chip doesn’t support flow control ability 0, RO/P 100BASE-T4 Support 1 = 100BASE-T4 is supported by the local device 0 = 100BASE-T4 is not supported The DM9302 does not support 100BASE-T4 so this bit is permanently set 100BASE-TX Full Duplex Support 1 = 100BASE-TX full duplex is supported by the local device ...
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... Local Device Next Page Able NP_ABLE = 1: DM9302, next page available NP_ABLE = 0: DM9302, no next page DM9302 does not support this function, so this bit is always New Page Received A new link code word page received. This bit will be automatically cleared when the register (register 6) is read by management ...
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... Writing this bit will cause PHY entering the Sleep mode and power down all circuit except oscillator and clock generator circuit. When waking up from Sleep mode (write this bit to 0), the configuration will go back to the state before sleep; but the state machine will be reset DM9302 Description 43 ...
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... Ability match Acknowledge match Acknowledge match fail Consistency match Consistency match fail Parallel detects signal link ready Parallel detects signal link ready fail Auto-negotiation completed successfully Description DM9302 Preliminary datasheet DM9302-15-DS-P01 July 30, 2009 ...
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... Link pulses disabled, good link condition forced This bit is valid only in 10Mbps operation Heartbeat Enable 1 = Heartbeat function enabled 0 = Heartbeat function disabled When the DM9302 is configured for full duplex operation, this bit will be ignored (the collision/heartbeat function is invalid in full duplex mode) Squelch Enable 1 = Normal squelch ...
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... Manual force MDI/MDIX. 0: Enable HP Auto-MDIX 1: Disable HP Auto-MDIX , MDIX_CNTL value depend on Reg.14H.bit5 0,RW Vendor monitor select 1 0,RW Vendor monitor select 0 0,RW Reserved Force application. 0,RW Power down control value Decision the value of each field Reg.13H. 1: power down 0: normal DM9302 Description Preliminary datasheet DM9302-15-DS-P01 July 30, 2009 ...
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... TX amplitude is reduced for power saving. 0: disable Transmit amplitude reduce function 0.RW Transmit Power Saving Control Disabled 1: when cable is unconnected with link partner, the driving current of transmit is reduced for power saving. 0: disable transmit driving power saving function 0,RO RESERVED DM9302 Description Description Description 47 ...
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... The memory write address (register FAh/FBh) and the memory read address (register F4h/F5h) represent the physical memory address of the DM9302 internal memory noted that after the memory had been written by memory write command, the switch reset command (bit 6 of register 52h) ...
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... Full Duplex Flow Control The DM9302 supports half-duplex backpressure. The inducement is the same as full duplex mode. When flow control is required, the DM9302 sends jam pattern, thus forcing a collision. The flow control ability can be set in bit 4 of register 61h. 9.2.9 Partition Mode The DM9302 provides a partition mode for each port, see bit 6 of register 61h ...
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... Broadcast Storm Filtering The DM9302 has an option to limit the traffic of broadcast or multicast packets, to protect the switch from lower bandwidth availability. There are two type of broadcast storm control, one is throttling broadcast packet only, the other includes multicast ...
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... VID 12 bits The DM9302 will remove the tag from the (3). Receive untagged packet and forward to Tag The DM9302 will insert the PVID tag when an (4). Receive tagged packet and forward to Tag Received packet will forward to destination port 9.2.14 Priority Support The DM9302 supports Quality of Service (QoS) ...
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... Ethernet Fiber/Twisted Pair Media Converter with Local bus Round-Robin 6Dh enabled by default. The DM9302 extracts 3-bit priority field from received packet with 802.1p VLAN tag, and maps this field against VLAN Priority Map Registers (D0h~D1h) to determine which transmit queue is designated. The VLAN Priority Map is programmable ...
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... MLT-3 Driver The two binary data streams created at the MLT-3 converter are fed to the twisted pair output driver, which converts these streams to current sources and alternately transformer’s primary winding, resulting in a minimal current MLT-3 signal. DM9302 drives either side of the transmit ...
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... DM9302 5B Code 43210 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 11111 11000 10001 01101 00111 00100 00000 00001 00010 00011 00101 00110 01000 01100 10000 11001 Preliminary datasheet DM9302-15-DS-P01 July 30, 2009 ...
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... DM9302-15-DS-P01 July 30, 2009 10/100Mbps Ethernet Fiber/Twisted Pair Media Converter with Local bus 9.3.2.3 MLT-3 to NRZI Decoder The DM9302 decodes the MLT-3 information from the Digital Adaptive Equalizer into NRZI data. 9.3.2.4 Clock Recovery Module The Clock Recovery Module accepts NRZI data from the MLT-3 to NRZI decoder ...
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... The T/R symbol pair is also stripped from the nibble, presented to the Reconciliation layer. 9.3.3 10Base-T Operation The 10Base-T transceiver is IEEE 802.3u compliant. When the DM9302 is operating in 10Base-T mode, the coding scheme is Manchester. Data processed for transmit is presented in nibble format, converted to a serial bit stream, then the Manchester encoded. ...
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... DM9302 Conditions - - - - - - - Lead-free Device Conditions - - - - 1.8VD only 1.8VA only 3.3VD only 3.3VA only 1.8VD only 1.8VA only 3.3VD only 3.3VA only 1.8VD only 1.8VA only 3.3VD only 3.3VA only 1.8VD only 1.8VA only 3 ...
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... Max. Unit Conditions - 0 VIN = 0.0V, Vcond1 - 1 uA VIN = 3.3V, Vcond1 - 0.4 V IOL =4mA - - V IOH = -4mA - V 100 Ω Termination 2.1 V Peak to Peak 5.6 V Peak to Peak │21│ mA Absolute Value │56│ mA Absolute Value DM9302 Vcond1 Vcond1 Across Preliminary datasheet DM9302-15-DS-P01 July 30, 2009 ...
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... PWRST# high to EECS high T4 PWRST# high to EECS burst end T5 PWRST# high to CS# available Preliminary datasheet DM9302-15-DS-P01 July 30, 2009 10/100Mbps Ethernet Fiber/Twisted Pair Media Converter with Local bus T1 Min Typ. Max. Unit Conditions - - 400 -- us DM9302 - - - - - 59 ...
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... IOR# width T4 IOR# invalid to next IOR#/IOW# valid When read DM9302 register T4 IOR# invalid to next IOR#/IOW# valid When read DM9302 memory with F0h register T3+T4 IOR# invalid to next IOR#/IOW# valid When read DM9302 memory with F2h register T5 System Data(SD) Delay time T6 IOR# invalid to System Data(SD) invalid *1 : the Unit: clk is under the internal system clock 50MHz ...
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... T3 IOW# Width T4 IOW# Invalid to next IOW#/IOR# valid When write DM9302 INDEX port T4 IOW# Invalid to next IOW#/IOR# valid When write DM9302 DATA port T3+T4 IOW# Invalid to next IOW#/IOR# valid When write DM9302 memory T5 System Data(SD) Setup Time T6 System Data(SD) Hold Time *1 : the Unit: clk is under the internal system clock 50MHz ...
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... EEDIO Setup Time in input state T7 EEDIO Hold Time in input state 62 10/100Mbps Ethernet Fiber/Twisted Pair Media Converter with Local bus Parameter DM9302 Min. Typ. Max. 480 2080 0.38 460 2100 8 8 Preliminary datasheet DM9302-15-DS-P01 T2 Unit ns ns MHz July 30, 2009 ...
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... TYP o 12 TYP and E do not include resin fin DM9302 Dimension in inch Min Nom Max - - 0.063 0.002 - 0.006 0.053 0.055 0.057 0.007 0.009 0.011 0.007 0.008 0.009 0.004 - 0.008 0.004 - 0.006 0.472 BSC 0.394 BSC ...
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... Ethernet networking standards. DM9302 Semiconductor Inc. develops Our currently Preliminary datasheet DM9302-15-DS-P01 and July 30, 2009 ...