dm9302 Davicom Semiconductor, Inc., dm9302 Datasheet - Page 17

• Manufacturer Part Number: dm9302
• Description: 10/100mbps Ethernet Fiber/twisted Pair Media Converter With Local Bus
• Manufacturer: Davicom Semiconductor, Inc.

Key to Default
In the register description that follows, the default column
takes the form:
<Reset Value>, <Access Type>
Where:
<Reset Value>:
P = power on reset, by PWRST# pin, default value
H = hardware reset, by Reg. 52H bit 6, default value
S = software reset, by Reg. 00H bit 0, default value
6.1 Network Control Register (00H)
6.2 Network Status Register (01H)
Preliminary datasheet
DM9302-15-DS-P01
July 30, 2009
1
0
X
4:2
7:6
1:0
Bit
Bit
7
6
5
1
0
5
4
3
2
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
LINK_X_ST
LNK_X_EN
TX2END
TX1END
Name
Name
CLR1
Bit set to logic one
Bit set to logic zero
No default value
RST
LBK
PH0,RW
PH0,RW
PH0,RW
Default
RW/C1
RW/C1
Default
PHS0,
PHS0,
W/C1
0,RO
0,RO
0,RO
PH0,
0,RO
0,RO
PH0,
RW
10/100Mbps Ethernet Fiber/Twisted Pair Media Converter with Local bus
Reserved
Link Change Status.
This bit is set after port 0 or 1 link changed.
If bit 5 of NCR is set, this bit is cleared by write 1; Otherwise it can be cleared by
read or write 1.
Reserved
TX Packet 2 Complete Status.
This bit is set after transmit completion of packet index 2
If bit 5 of NCR is set, this bit is cleared by write 1; Otherwise it can be cleared by
read or write 1.
TX Packet 1 Complete status.
This bit is set after transmit completion of packet index 1
If bit 5 of NCR is set, this bit is cleared by write 1; Otherwise it can be cleared by
read or write 1.
Reserved
Reserved
Link Change Status Enable
When set, it enables to report port 0 or 1 link change status function. Clearing this
bit will also clear link change status
This bit will not be affected after a software reset
0: REG. 01H auto-cleared after read
1: REG. 01H cleared by writing 1 to respected bit.
Reserved
Loopback test Mode
All transmit packets from processor port are forward to processor port itself.
Software reset and auto clear after 10us
E = default value from EEPROM setting
T = default value from strap pin
<Access Type>:
RO = Read only
RW = Read/Write
R/C = Read and Clear
RW/C1=Read/Write and Cleared by write 1
WO = Write only
Reserved bits should be written with 0.
Reserved bits are undefined on read access.
Description
Description
DM9302
17