dm9000bi Davicom Semiconductor, Inc., dm9000bi Datasheet
dm9000bi
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... DAVICOM Semiconductor, Inc. Industrial-grade Ethernet Controller With General Processor Interface Preliminary Version: DM9000BI-13-DS-P02 January 17, 2008 Industrial-grade Ethernet Controller with General Processor Interface DM9000BI DATA SHEET DM9000BI Preliminary Version: DM9000BI-DS-P02 January 17, 2008 1 ...
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... Flow Control Threshold Register ( 09H ) .................................................................................................. 17 6.11 RX/TX Flow Control Register ( 0AH )........................................................................................................ 18 6.12 EEPROM & PHY Control Register ( 0BH ) ............................................................................................... 18 6.13 EEPROM & PHY Address Register ( 0CH ).............................................................................................. 18 6.14 EEPROM & PHY Data Register (EE_PHY_L:0DH Preliminary Version: DM9000BI-13-DS-P02 January 17, 2008 Industrial-grade Ethernet Controller with General Processor Interface Content EE_PHY_H:0EH) ................................................. 18 DM9000BI ...
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... Memory data write command with address increment Register (F8H)..................................................... 25 6.43 Memory data write address Register (FAH~FBH)..................................................................................... 25 6.44 TX Packet Length Register (FCH~FDH)................................................................................................... 25 6.45 Interrupt Status Register (FEH)................................................................................................................. 25 6.46 Interrupt Mask Register (FFH) .................................................................................................................. 25 7. EEPROM Format .............................................................................................................. 26 8. PHY Register Description ............................................................................................... 27 Preliminary Version: DM9000BI-13-DS-P02 January 17, 2008 Industrial-grade Ethernet Controller with General Processor Interface DM9000BI 3 ...
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... Adaptive Equalization .......................................................................................................................... 41 9.6.3 MLT-3 to NRZI Decoder ....................................................................................................................... 41 9.6.4 Clock Recovery Module....................................................................................................................... 41 9.6.5 NRZI to NRZ ........................................................................................................................................ 41 9.6.6 Serial to Parallel................................................................................................................................... 41 9.6.7 Descrambler......................................................................................................................................... 41 9.6.8 Code Group Alignment ........................................................................................................................ 42 9.6.9 4B5B Decoder...................................................................................................................................... 42 9.7 10Base-T Operation .................................................................................................................................... 42 9.8 Collision Detection ...................................................................................................................................... 42 9.9 Carrier Sense .............................................................................................................................................. 42 9.10 Auto-Negotiation........................................................................................................................................ 42 9.11 Power Reduced Mode............................................................................................................................... 43 Preliminary Version: DM9000BI-13-DS-P02 January 17, 2008 Industrial-grade Ethernet Controller with General Processor Interface DM9000BI 4 ...
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... Non Auto MDIX Transformer Application ) ........................................................ 50 11.4 Power Decoupling Capacitors ................................................................................................................... 51 11.5 Ground Plane Layout ................................................................................................................................ 52 11.6 Power Plane Partitioning ........................................................................................................................... 53 11.7 Magnetic Specification Requirements ....................................................................................................... 54 11.8 Crystal Selection Guide ............................................................................................................................. 54 12. Package Information ..................................................................................................... 55 13. Ordering Information..................................................................................................... 56 Preliminary Version: DM9000BI-13-DS-P02 January 17, 2008 Industrial-grade Ethernet Controller with General Processor Interface ° ° +85 C) ........................................................................................... 44 DM9000BI 5 ...
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... UTP3 10Base-T and UTP5 in 100Base-TX with HP Auto-MDIX fully compliant with the IEEE 802.3u Spec. Its auto-negotiation function will automatically configure the DM9000BI to take the maximum advantage of its abilities. The DM9000BI also supports IEEE 802.3x full- duplex flow control. LED 100 Base-TX ...
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... Integrated 16K Byte SRAM ■ Build in 3.3V to 1.8V regulator ■ Supports IP/TCP/UDP checksum generation and checking Preliminary Version: DM9000BI-13-DS-P02 January 17, 2008 Industrial-grade Ethernet Controller with General Processor Interface ■ Supports early Transmit ■ Supports automatically load vendor ID and product ID from EEPROM ■ ...
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... Pin Configuration 4.1 (16-bit mode) CS# LED2 LED1 PWRST# TEST VDD X2 X1 GND SD RXGND BGGND Preliminary Version: DM9000BI-13-DS-P02 January 17, 2008 Industrial-grade Ethernet Controller with General Processor Interface DM9000BI 42 (16-bit mode DM9000BI 24 SD14 VDD 23 22 SD15 21 EECS 20 EECK ...
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... CS# LED2 LED1 PWRST# TEST VDD X2 X1 GND SD RXGND BGGND Preliminary Version: DM9000BI-13-DS-P02 January 17, 2008 Industrial-grade Ethernet Controller with General Processor Interface DM9000BI 42 (8-bit mode DM9000BI 24 LED3 VDD 23 22 WAKE 21 EECS 20 EECK EEDIO 19 SD0 ...
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... This pin is low active at default, its polarity can be modified by EEPROM setting. See the EEPROM content description for detail Chip Select A default low active signal used to select the DM9000BI. Its polarity can I,PD be modified by EEPROM setting. See the EEPROM content description for detail. ...
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... BGGND 1 BGRES 2 RXVDD18 9 TXVDD18 Preliminary Version: DM9000BI-13-DS-P02 January 17, 2008 Industrial-grade Ethernet Controller with General Processor Interface General I/O Ports I/O Registers GPCR and GPR can program these pins These pins are input ports at default. Type Clock to EEPROM This pin is also used as the strap pin of the polarity of the INT pin When this pin is pulled high, the INT pin is low active ...
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... These two pins are the transmit output in MDI mode or the receive input in MDIX mode. Type Operation Mode I Force to ground in normal application Power on Reset I Active low signal to initiate the DM9000BI The DM9000BI is ready after 5us when this pin deasserted Type Digital VDD P 3.3V power input Digital GND P DM9000BI Description ...
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... Vendor Control and Status Register Set The DM9000BI implements several control and status registers, which can be accessed by the host. These CSRs Register NCR Network Control Register NSR Network Status Register TCR TX Control Register TSR I TX Status Register I TSR II TX Status Register II ...
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... FDX PS0,RO PS00, 2:1 LBK RW 0 RST P0,RW Preliminary Version: DM9000BI-13-DS-P02 January 17, 2008 Industrial-grade Ethernet Controller with General Processor Interface T = default value from strap pin <Access Type> Read only RW = Read/Write R/C = Read and Clear RW/C1=Read/Write and Cleared by write Write only Reserved bits are shaded and should be written with 0. ...
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... EC PS0,RO 1:0 RESERVED 0,RO Preliminary Version: DM9000BI-13-DS-P02 January 17, 2008 Industrial-grade Ethernet Controller with General Processor Interface Media Speed 0:100Mbps 1:10Mbps, when Internal PHY is used. This bit has no meaning when LINKST=0 Link Status 0:link failed 1:link OK, Wakeup Event Status. Clears by read or write 1 (work in 8-bit mode) ...
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... CE PS0,RO 0 FOE PS0,RO Preliminary Version: DM9000BI-13-DS-P02 January 17, 2008 Industrial-grade Ethernet Controller with General Processor Interface Transmit Jabber Time Out It is set to indicate that the transmitted frame is truncated due to more than 2048 bytes are transmitted Loss of Carrier It is set to indicate the loss of carrier during the frame transmission not valid in ...
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... HWOT PS3, RW 3:0 LWOT PS8, RW Preliminary Version: DM9000BI-13-DS-P02 January 17, 2008 Industrial-grade Ethernet Controller with General Processor Interface Receive Overflow Counter Overflow This bit is set when the ROC has an overflow condition Receive Overflow Counter This is a statistic counter to indicate the received packet count upon FIFO overflow Back Pressure High Water Overflow Threshold ...
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... DA matches and RX SRAM is over BPHW of register 8. RX Pause Packet Status, latch and read clearly RX Pause Packet Current Status Flow Control Enable Set to enable the flow control mode (i.e. can disable DM9000BI TX function) Reserved Reload EEPROM. Driver needs to clear it up after the operation completes Write EEPROM Enable EEPROM or PHY Operation Select When reset, select EEPROM ...
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... GPC31 000,RW 0 RESERVED P1,RO Preliminary Version: DM9000BI-13-DS-P02 January 17, 2008 Industrial-grade Ethernet Controller with General Processor Interface Reserved When set, it enables Link Status Change Wake up Event This bit will not be affected after software reset When set, it enables Sample Frame Wake up Event This bit will not be affected after software reset ...
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... LED P0,RW 6 RLCP P0,RW Preliminary Version: DM9000BI-13-DS-P02 January 17, 2008 Industrial-grade Ethernet Controller with General Processor Interface Reserved General Purpose Output 6~4 (in 8-bit mode) These bits are reflect to pin GP6~4 respectively. General Purpose (in 8-bit mode) When the correspondent bit of General Purpose Control Register is 1, the value of the bit is reflected to pin GP3~1 respectively ...
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... P0,RW 1 FB1 P0,RW 0 FB0 P0,RW Preliminary Version: DM9000BI-13-DS-P02 January 17, 2008 Industrial-grade Ethernet Controller with General Processor Interface Disable TX Under run Retry Disable to re-transmit the underruned packet One Packet Mode When set, only one packet transmit command can be issued before transmit completed. When cleared, at most two packet transmit command can be issued before transmit completed ...
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... IPP PS0,RO 1 RCSEN PS0,RW 0 DCSE PS0,RW Preliminary Version: DM9000BI-13-DS-P02 January 17, 2008 Industrial-grade Ethernet Controller with General Processor Interface Early Transmit Enable Enable bits[2:0] Early Transmit Status II Early Transmit Status I Reserved Early Transmit Threshold Start transmit when data write to TX FIFO reach the byte-count threshold ...
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... IOW_SPIKE P0,RW 0 IOR_SPIKE P1,RW Preliminary Version: DM9000BI-13-DS-P02 January 17, 2008 Industrial-grade Ethernet Controller with General Processor Interface External PHY Address Enabled When register 34H bit 0 is set to ‘1’, the PHY address field in MII Management Interface format is defined at bit 4~0. External PHY Address Bit 4~0 The PHY address field in MII Management Interface format ...
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... ON Read data from RX SRAM. After the read of this command, the read pointer of internal SRAM is unchanged. And the DM9000BI starts to pre-fetch the SRAM data to internal data buffers. Read data from RX SRAM. After the read of this command, the read pointer of internal SRAM is unchanged Read data from RX SRAM ...
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... PTI PS0,RW 0 PRI PS0,RW Preliminary Version: DM9000BI-13-DS-P02 January 17, 2008 Industrial-grade Ethernet Controller with General Processor Interface Write Data to TX SRAM After the write of this command, the write pointer is increased depends on the operator mode. (8-bit or 16-bit respectively) Memory Data Write_ address High Byte ...
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... Vendor ID 4 Product ID 5 pin control 6 Wake-up mode control 7 Preliminary Version: DM9000BI-13-DS-P02 January 17, 2008 Industrial-grade Ethernet Controller with General Processor Interface offset 0~5 6 Byte Ethernet Address Bit 1:0=01: Update vendor ID and product ID Bit 3:2=01: Accept setting of WORD6 [8:0] Bit 5:4=01: reserved Bit 7:6=01: Accept setting of WORD7 [3:0] (in 8-bit mode) ...
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... Value>, <Access Type> / <Attribute(s)> Where： <Reset Value>: 1 Bit set to logic one 0 Bit set to logic zero X No default value <Access Type>: Preliminary Version: DM9000BI-13-DS-P02 January 17, 2008 Industrial-grade Ethernet Controller with General Processor Interface Power Isolate Restart Full Coll ...
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... When auto-negotiation is disabled (bit 12 of this register cleared), this bit has no function and it should be cleared. This bit is self-clearing and it will keep returning to a value of 1 until auto-negotiation is initiated by the DM9000BI. The operation of the auto-negotiation process will not be affected by the management entity that clears this bit ...
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... DM9000BI is not able to perform 100BASE-TX in half duplex mode 1,RO/P 10BASE-T Full Duplex Capable 1 = DM9000BI is able to perform 10BASE-T in full duplex mode 0 = DM9000BI is not able to perform 10BASE-TX in full duplex mode 1,RO/P 10BASE-T Half Duplex Capable 1 = DM9000BI is able to perform 10BASE-T in half duplex mode 0 = DM9000BI is not able to perform 10BASE-T in half duplex mode ...
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... Extended capability 8.3 PHY ID Identifier Register #1 (PHYID1 The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM9000BI. The Identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), a vendor's model number, and a model revision number. DAVICOM Semiconductor's IEEE assigned OUI is 00606E. ...
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... Auto-negotiation Advertisement Register (ANAR This register contains the advertised abilities of this DM9000BI device as they will be transmitted to its link partner during Auto-negotiation. Bit Bit Name 4.15 NP 4.14 ACK 4.13 RF 4.12 Reserved -4.11 4.10 FCS 4.9 T4 4.8 TX_FDX 4.7 TX_HDX 4.6 10_FDX 4.5 10_HDX 4.4-4.0 Selector <00001>, RW Protocol Selection Bits Preliminary Version: DM9000BI-13-DS-P02 January 17, 2008 ...
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... Link partner, next page available 0, RO Acknowledge 1 = Link partner ability data reception acknowledged 0 = Not acknowledged The DM9000BI's auto-negotiation state machine will automatically control this bit from the incoming FLP bursts. Software should not attempt to write to this bit 0, RO Remote Fault 1 = Remote fault indicated by link partner ...
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... Local Device Next Page Able NP_ABLE = 1: DM9000BI, next page available NP_ABLE = 0: DM9000BI, no next page DM9000BI does not support this function, so this bit is always 0 0, RO/LH New Page Received A new link code word page received. This bit will be automatically cleared when the register (register 6) is read by management ...
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... Reserved 0, RO -17.9 17.8 PHYADR[4 (PHYADR), PHY Address Bit 4:0 Preliminary Version: DM9000BI-13-DS-P02 January 17, 2008 Industrial-grade Ethernet Controller with General Processor Interface Reset State Machine 0, RW When writes 1 to this bit, all state machines of PHY will be reset. This bit is self-clear after reset is completed ...
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... This bit is valid only in 10Mbps operation Heartbeat Enable 1 = Heartbeat function enabled 0 = Heartbeat function disabled When the DM9000BI is configured for full duplex operation, this bit will be ignored (the collision/heartbeat function is invalid in full duplex mode), This bit is valid only in 10Mbps operation. Squelch Enable ...
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... MonSel1 20.2 MonSel0 20.1 Reserved 20.0 PD_value Preliminary Version: DM9000BI-13-DS-P02 January 17, 2008 Industrial-grade Ethernet Controller with General Processor Interface Reserved Read as 0, ignore on write Vendor power down control test Vendor power down control test Vendor power down control test Vendor power down control test ...
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... Preliminary Version: DM9000BI-13-DS-P02 January 17, 2008 Industrial-grade Ethernet Controller with General Processor Interface Decision the value of each field Register 19. 1: power down 0: normal DM9000BI 37 ...
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... Functional Description 9.1 Host Interface The host interface is a general processor local bus that using chip select (pin CS#) to access DM9000BI. Pin CS# is default low active which can be re-defined by EEPROM setting. There are only two addressing ports through the access of the host interface. One port is the INDEX port and the other is the DATA port ...
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... IDLEs into the transmit data stream until Transmit Enable is asserted and the next transmit packet is detected. The DM9000BI includes a Bypass 4B5B conversion option within the 100Base-TX Transmitter for support of applications like 100 Mbps repeaters which do not Require 4B5B conversion. ...
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... Preliminary Version: DM9000BI-13-DS-P02 January 17, 2008 Industrial-grade Ethernet Controller with General Processor Interface Meaning 4B code 3210 Data 0 0000 Data 1 0001 Data 2 0010 Data 3 0011 Data 4 0100 Data 5 0101 Data 6 0110 Data 7 ...
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... Version: DM9000BI-13-DS-P02 January 17, 2008 Industrial-grade Ethernet Controller with General Processor Interface 9.6.3 MLT-3 to NRZI Decoder The DM9000BI decodes the MLT-3 information from the Digital Adaptive Equalizer into NRZI data. 9.6.4 Clock Recovery Module The Clock Recovery Module accepts NRZI data from the MLT-3 to NRZI decoder. The Clock Recovery Module locks onto the data stream and extracts the 125 MHz reference clock ...
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... The T/R symbol pair is also stripped from the nibble, presented to the Reconciliation layer. 9.7 10Base-T Operation The 10Base-T transceiver is IEEE 802.3u compliant. When the DM9000BI is operating in 10Base-T mode, the coding scheme is Manchester. Data processed for transmit is presented in nibble format, converted to a serial bit stream, then the Manchester encoded. ...
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... Power Reduced Mode The Signal detect circuit is always turned to monitor whether there is any signal on the media (cable disconnected). The DM9000BI automatically turns off the power and enters the Power Reduced mode, whether its operation mode is N-way or force mode. When enters the Power Reduced mode, the transmit circuit still sends out fast link pules with minimum power consumption ...
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... Differential Output TD100 Voltage V 10TX+/- Differential Output Voltage TD10 I 100TX+/- Differential Output TD100 Current I 10TX+/- Differential Output Current TD10 Preliminary Version: DM9000BI-13-DS-P02 January 17, 2008 Industrial-grade Ethernet Controller with General Processor Interface Parameter Min. -0.3 -0.5 -0.3 -65 -40 － Min. 3.135 --- --- ...
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... T4 PWRST# high to EECS burst end Note: The DM9000BI needs the time about 3ms to down load the setting from EEPROM after PWRST# deasserted, During the period, the CS# pin is not recognized even no EEPROM present. So, please note that processor only access DM9000BI after PWRST# deasserted 3ms. ...
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... IOR# invalid to next IOR#/IOW# valid 6 When read DM9000BI register T +T IOR# valid to next IOR#/IOW# valid 2 6 When read DM9000BI memory with F0h register T +T IOR# valid to next IOR#/IOW# valid 2 6 When read DM9000BI memory with F2h register T CS#,CMD valid to IO16 valid ...
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... IOW# Invalid to CS#,CMD Invalid 5 T IOW# Invalid to next IOW#/IOR# valid 6 When write DM9000BI INDEX port T IOW# Invalid to next IOW#/IOR# valid 6 When write DM9000BI DATA port T +T IOW# Invalid to next IOW#/IOR# valid 2 6 When write DM9000BI memory T CS#,CMD Valid to IO16 valid ...
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... T EEDIO Setup Time when output 4 T5 EEDIO Hold Time when output T EEDIO Setup Time when input 6 T EEDIO Hold Time when input 7 Preliminary Version: DM9000BI-13-DS-P02 January 17, 2008 Industrial-grade Ethernet Controller with General Processor Interface Parameter DM9000BI Min. Typ. ...
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... Place the transformer as close as possible to the RJ-45 connector. Place all the 50Ω resistors as close as possible to the DM9000BI RXI± and TXO± pins. Traces routed from RXI± and TXO± to the transformer should run in close pairs directly to the transformer. The designer should be careful not to cross the transmit and receive pairs ...
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... Non Auto MDIX Transformer Application ) Preliminary Version: DM9000BI-13-DS-P02 January 17, 2008 Industrial-grade Ethernet Controller with General Processor Interface Figure 11-2 Non Auto MDIX Transformer Application DM9000BI 50 ...
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... Power Decoupling Capacitors Davicom Semiconductor recommends placing all the decoupling capacitors for all power supply pins as close as possible to the power pads of the DM9000BI (The best placed distance is < 3mm from pin). The recommended decoupling capacitor is 0.1µF or 0.01µF, as required by the design layout. ...
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... EMI. Ground plane partitioning can cause increased EMI emissions that could make the network interface card not comply with specific FCC Preliminary Version: DM9000BI-13-DS-P02 January 17, 2008 Industrial-grade Ethernet Controller with General Processor Interface regulations (part 15). Figure 11-4 shows a recommended ground layout scheme ...
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... Power Plane Partitioning The power planes should be approximately illustrated in Figure 11-5. Preliminary Version: DM9000BI-13-DS-P02 January 17, 2008 Industrial-grade Ethernet Controller with General Processor Interface Figure 11-5 Power Plane Partitioning DM9000BI 53 ...
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... A crystal can be used to generate the 25MHz reference clock instead of an oscillator. The crystal must be a fundamental type, and series-resonant. Preliminary Version: DM9000BI-13-DS-P02 January 17, 2008 Industrial-grade Ethernet Controller with General Processor Interface qualify all magnetic specifications before using them in an application. Industrial-temperature range, RoHS ...
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... D 0.354BSC D1 0.276BSC E 0.354BSC E1 0.276BSC 0.020BSC L 0.018 0.024 0.030 L1 0.039REF y 0.003MAX Preliminary Version: DM9000BI-13-DS-P02 January 17, 2008 Industrial-grade Ethernet Controller with General Processor Interface Notes: Dimensions determined at seating plane. Min. Nom. Max 1.60 2. Dimensions D1 and E 1do not include mold 0.05 - 0.15 protrusion ...
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... Conditions beyond those listed for the absolute maximum may destroy or damage the products. In addition, conditions for sustained periods at near the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and/or function. Preliminary Version: DM9000BI-13-DS-P02 January 17, 2008 Industrial-grade Ethernet Controller with General Processor Interface application circuits illustrated in this document are for reference purposes only ...