DM9008AEP_06 DAVICOM [Davicom Semiconductor, Inc.], DM9008AEP_06 Datasheet - Page 3
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DM9008AEP_06
Manufacturer Part Number
DM9008AEP_06
Description
Ethernet Controller with General Processor Interface
Manufacturer
DAVICOM [Davicom Semiconductor, Inc.]
Datasheet
1.DM9008AEP_06.pdf
(50 pages)
7. EEPROM Format .............................................................................................................. 26
8. MII Register Description.................................................................................................. 27
Preliminary
Version: DM9008A-DS-P02
Apr. 11, 2006
6.18 General purpose control Register ( 1EH ) (in 8-bit mode) ................................................................. 18
6.19 General purpose Register ( 1FH ) ........................................................................................................ 19
6.20 TX SRAM Read Pointer Address Register (22H~23H) ........................................................................ 19
6.21 RX SRAM Write Pointer Address Register (24H~25H) ........................................................................ 19
6.22 Vendor ID Register (28H~29H) ............................................................................................................ 19
6.23 Product ID Register (2AH~2BH)........................................................................................................... 19
6.24 Chip Revision Register (2CH)............................................................................................................... 19
6.25 Transmit Control Register 2 ( 2DH ) ..................................................................................................... 19
6.26 Operation Test Control Register ( 2EH ) .............................................................................................. 20
6.27 Special Mode Control Register ( 2FH )................................................................................................. 20
6.28 Early Transmit Control/Status Register ( 30H ) .................................................................................... 21
6.29 Check Sum Control Register ( 31H ) .................................................................................................... 21
6.30 Receive Check Sum Status Register ( 32H ) ....................................................................................... 21
6.31 LED Pin Control Register ( 34H ).......................................................................................................... 21
6.32 Processor Bus Control Register ( 38H ) ............................................................................................... 22
6.33 INT Pin Control Register ( 39H )........................................................................................................... 23
6.34 System Clock Turn ON Control Register ( 50H ).................................................................................. 23
6.35 Resume System Clock Control Register ( 51H ) .................................................................................. 23
6.36 Memory Data Pre-Fetch Read Command without Address Increment Register (F0H) ....................... 24
6.37 Memory Data Read Command without Address Increment Register (F1H) ........................................ 24
6.38 Memory Data Read Command with Address Increment Register (F2H) ............................................. 24
6.39 Memory Data Read_address Register (F4H~F5H) .............................................................................. 24
6.40 Memory Data Write Command without Address Increment Register (F6H)......................................... 24
6.41 Memory data write command with address increment Register (F8H) ................................................ 24
6.42 Memory data write_address Register (FAH~FBH)............................................................................... 24
6.43 TX Packet Length Register (FCH~FDH) .............................................................................................. 24
6.44 Interrupt Status Register (FEH) ............................................................................................................ 25
6.45 Interrupt Mask Register (FFH) .............................................................................................................. 25
8.1 Basic Mode Control Register (BMCR) - 00............................................................................................. 27
8.2 Basic Mode Status Register (BMSR) - 01 .............................................................................................. 29
8.3 PHY ID Identifier Register #1 (PHYID1) - 02.......................................................................................... 30
8.4 PHY ID Identifier Register #2 (PHYID2) - 03.......................................................................................... 30
Ethernet Controller with General Processor Interface
DM9008AEP
3