AX88871AP ASIX [ASIX Electronics Corporation], AX88871AP Datasheet - Page 5

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AX88871AP

Manufacturer Part Number
AX88871AP
Description
10/100BASE Dual Speed Bripeater Controller
Manufacturer
ASIX [ASIX Electronics Corporation]
Datasheet
1.2 Features
1. Minimum 32K bytes, maximum 256K bytes SRAM to buffer packets
2. Seamless buffer management without waste any space of buffer memory
3. Simple asynchronous 8-bit SRAM interface to reduce system cost
4. 256 or 1024 entries is supported
5. Auto learning and filtering
6. Two forwarding modes are supported : Store-n-Forward and fragment-free
7. Flow-control is supported optionally.
8. Buffer RAM auto testing
9. Routing and Learning at wire speed (148810 packets/sec at 100Mbps)
AX88871AP Bripeater
IEEE 802.3u repeater compatible
Supports per port 10/100Mbps alternative with auto detected
Build in 10/100Mbps Bridge engine with following features
Supports 8 10/100Mbps network connections
8 dedicated MII interfaces can support 100BASE-TX/T4/FX PHY interfaces
Port 7 and/or 8 can connect to bridge, switch or MAC type device optionally.
Up-to 8 repeater chips can be cascaded for large HUB application(old method)
Up-to 6 repeaters can be cascaded for vertical expansion(new feature)
Up-to 4 chips can be cascaded locally for horizontal expansion(new feature)
Support two application mode : single or cascade
Low latency design supports Class II repeater implementation with large port number
All ports can be separately isolated or partitioned in response to fault condition
Separate jabber and partition state machines for each port
Per-port LED display for Jabber, Partition, Activity. Global partition, RAM test fail and
collision, utilization (%) for 10/100Mbps presentation
Power on LED diagnosis. All the LED display will follow the “ON-OFF-ON-OFF-Normal”
operation procedure during/after power on reset
208-pin PQFP
5
ASIX ELECTRONICS CORPORATION

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