AX88871AP ASIX [ASIX Electronics Corporation], AX88871AP Datasheet - Page 9

• Manufacturer Part Number: AX88871AP
• Description: 10/100BASE Dual Speed Bripeater Controller
• Manufacturer: ASIX [ASIX Electronics Corporation]

2.0 Pin Description
The following terms describe the AX88871A pinout:
All pin names with the “/” suffix are asserted low.
2.1 MII interfaces
TXER[7:0]
or
COL[7:0]
TXD[7:0][3:0]
TXEN[7:0]
RXD[7:0][3:0]
RXER[7:0]
RXCLK[7:0]
RXDV[7:0]
CRS[7:0]
COL_O[6]
COL_O[7]
Signal Name
I
O
I/O
AX88871AP Bripeater
Type
O
or
O
O
O
O
I
I
I
I
I
=
=
=
I
76, 59, 44, 29,
13, 205, 190,
88-85, 70-67
55-52, 39-36
83-80, 65-62
49-46, 34-31
27, 11, 203,
30, 14, 206,
28, 12, 204,
23-20, 8-5
18-15, 3-2
89, 72, 56
74, 57, 42
79, 61, 45
75, 58, 43
Pin No.
84, 66,51
40, 24, 9
202, 187
35, 19, 4
197, 180
188, 172
191, 175
189, 173
201-198
186-185
182-181
208-207
195-192
179-176
174
73
90
Input
Output
Input /Output
Transmit Error : When /HALF10 pin set to “high”. TXER is transition
synchronously with respect to the rising edge of TXCLK . Asserted
high when a code violation is request to be send
Collision : When /HALF10 pin set to “low”. COL is input from PHY,
when 10Mbps PHY is in half-duplex mode.
Transmit Data : TXD[3:0] is transition synchronously with respect to
the rising edge of TXCLK. For each TXCLK period in which TXEN is
asserted, TXD[3:0] are accepted for transmission by the PHY.
Transmit Enable : TXEN is transition synchronously with respect to the
rising edge of TXCLK. TXEN indicates that the port is presenting
nibbles on TXD [3:0] for transmission.
Receive Data : RXD [3:0] is driven by the PHY synchronously with
respect to RXCLK.
Receive Error : RXER ,is driven by PHY and synchronous to RXCLK,
is asserted for one or more RXCLK periods to indicate to the port that
an error has detected.
Receive Clock : RX_CLK is a continuous clock that provides the
timing reference for the transfer of the RXDV,RXD [3:0] and RXER
signals from the PHY to the MII port of the repeater.
Receive Data Valid : RX_DV is driven by the PHY synchronously with
respect to RXCLK. Asserted high when valid data is present on RXD
[3:0].
Carrier Sense : Asynchronous signal CRS is asserted by the PHY when
receive medium is non-idle at full duplex mode.
Collision : Collision detection signal for port 6
Collision : Collision detection signal for port 7
9
Description
ASIX ELECTRONICS CORPORATION