NM9805CV ETC [List of Unclassifed Manufacturers], NM9805CV Datasheet - Page 4

• Manufacturer Part Number: NM9805CV
• Description: PCI + 1284 Printer Port
• Manufacturer: ETC [List of Unclassifed Manufacturers]

Nm9805
PCI + 1284 Printer Port
Pin Name
Page 4
CLK
nRESET
AD31-29 126-128
AD28-24
AD23-16
AD15-11
AD10-8
AD7-0
nFRAME
nIRDY
nTRDY
nSTOP
nLOCK
IDSEL
nDEVSEL
nPERR
34-38
40-42
11-18
46-53
128
122
121
2-6
24
26
23
25
27
28
29
9
Type
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
I
I
I
I
I
I
Description
33 MHz PCI system clock input.
PCI system reset (active low). Resets all internal register, sequencers, and
signals to a consistent state. During reset condition AD31-0, nSER are three-
stated.
Multiplexed PCI address/data bus. A bus transaction consists of an address
phase followed by one or more data phases. During the address phase, AD31-
0 contain a physical address. Write data is stable and valid when nIRDY and
nTRDY are asserted (active).
See AD31-29 description.
See AD31-29 description.
See AD31-29 description.
See AD31-29 description.
Frame is driven by the current master to indicate the beginning and duration
of an access. nFRAME is asserted to indicate a bus transaction is beginning.
While nFRAME is active, data transfer continues.
Initiator Ready. During a write, nIRDY asserted indicates that the initiator is
driving valid data onto the data bus. During a read, nIRDY asserted indicates
that the initiator is ready to accept data from the Nm9805.
Target Ready (three-state). It is asserted when Nm9805 is ready to complete
the current data phase.
Nm9805 asserts nSTOP to indicate that it wishes the initiator to stop the
transaction in process on the current data phase.
Lock indicates an atomic operation that may require multiple transactions to
complete.
Initialization Device Select. It is used as a chip select during configuration
read and write transactions.
Device Select (three-state). Nm9805 asserts nDEVSEL when the Nm9805
has decoded its address.
Parity Error (three-state). Is used to report parity errors during all PCI trans-
See AD31-29 description.
Rev. 1.1