88E1111-XX-BAB-C000 MARVELL [Marvell Technology Group Ltd.], 88E1111-XX-BAB-C000 Datasheet - Page 18

• Manufacturer Part Number: 88E1111-XX-BAB-C000
• Description: Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
• Manufacturer: MARVELL [Marvell Technology Group Ltd.]

Table 5:
The RTBI interface supports 1000BASE-T mode of operation. The RTBI interface uses the same pins as the
RGMII interface. The MAC interface pins are 3.3V tolerant.
Doc. No. MV-S105540-00, Rev. --
Page 18
117-TFBGA
Pi n #
E2
H2
G3
G2
F1
E1
C1
B3
C3
D3
B2
B1
RTBI Interface
96 -BCC
Pin #
8
16
14
12
11
9
2
91
93
92
95
94
88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
128 -PQF P
P i n #
14
24
20
19
18
16
7
125
126
128
3
4
Document Classification: Proprietary Information
P i n N a m e
GTX
TXC
TXD[3]/TD[3]
TXD[2]/TD[2]
TXD[1]/TD[1]
TXD[0]/TD[0]
TX_EN/
TD4_TD9
RX_CLK/
RXC
RXD[3]/RD[3]
RXD[2]/RD[2]
RXD[1]/RD[1]
RXD[0]/RD[0]
RX_DV/
RD4_RD9
_
CLK/
P i n
Ty pe
I
I
I
O, Z
O, Z
O, Z
Des cription
RGMII Transmit Clock provides a 125 MHz
reference clock with ± 50 ppm tolerance. In
RTBI mode, GTX_CLK is used as TXC.
RTBI Transmit Data.
In RTBI mode, TXD[3:0] are used as
TD[3:0]. TD[3:0] run at double data rate with
bits [3:0] presented on the rising edge of
GTX_CLK, and bits [8:5] presented on the
falling edge of GTX_CLK. In this mode,
TXD[7:4] are ignored.
RTBI Transmit Data.
In RTBI mode, TX_EN is used as TD4_TD9.
TD4_TD9 runs at a double data rate with bit
4 presented on the rising edge of GTX_CLK,
and bit 9 presented on the falling edge of
GTX_CLK.
RTBI Receive Clock provides a 125 MHz ref-
erence clock with ± 50 ppm tolerance
derived from the received data stream. In
RTBI mode, RX_CLK is used as RXC.
RTBI Receive Data.
In RTBI mode, RXD[3:0] are used as
RD[3:0]. RD[3:0] runs at double data rate
with bits [3:0] presented on the rising edge of
RX_CLK, and bits [8:5] presented on the fall-
ing edge of RX_CLK. In this mode, RXD[7:4]
are ignored.
RTBI Receive Data.
In RTBI mode, RX_DV is used as
RD4_RD9. RD4_RD9 runs at a double data
rate with bit 4 presented on the rising edge
of RX_CLK, and bit 9 presented on the fall-
ing edge of RX_CLK.
Copyright © 2009 Marvell
March 4, 2009, Advance