K9F6408Q0C-H SAMSUNG [Samsung semiconductor], K9F6408Q0C-H Datasheet - Page 16

• Manufacturer Part Number: K9F6408Q0C-H
• Description: 8M x 8 Bit Bit NAND Flash Memory
• Manufacturer: SAMSUNG [Samsung semiconductor]

System Interface Using CE don’ t-care.
Figure 3. Program Operation with CE don’ t-care.
Timing requirements : If CE is is exerted high during data-loading,
tCS must be minimum 10ns and tWC must be increased accordingly.
Figure 4. Read Operation with CE don’ t-care.
For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal
528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for
voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read-
ing would provide significant savings in power consumption.
K9F6408Q0C
K9F6408U0C
I/O
I/O
CLE
CE
WE
ALE
R/B
CE
WE
WE
CLE
ALE
CE
RE
0
0
~
~
7
7
t
CS
00h
80h
Start Add.(3Cycle)
Start Add.(3Cycle)
t
WP
t
On K9F6408U0C_T,Q or K9F6408U0C_V,F
CE must be held
CH
low during tR
t
R
Data Input
16
I/O
CE
RE
0
~
Timing requirements : If CE is exerted high during sequential
data-reading, the falling edge of CE to valid data(tCEA) must
be kept greater than 45ns.
7
CE don’ t-care
CE don’ t-care
t
Data Output(sequential)
CEA
t
REA
FLASH MEMORY
Data Input
out
10h