MC10EP56MNG ON Semiconductor, MC10EP56MNG Datasheet - Page 2

• Manufacturer Part Number: MC10EP56MNG
• Description: IC MUX ECL DUAL DIFF 2:1 20-QFN
• Manufacturer: ON Semiconductor
• Series: 10EPr
• Type: Differential Digital Multiplexerr

Specifications of MC10EP56MNG

• Circuit: 2 x 2:1
• Independent Circuits: 1
• Voltage Supply Source: Dual Supply
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TFQFN Exposed Pad
• Product: Multiplexer
• Logic Family: ECL
• Number Of Lines (input / Output): 4.0 / 2.0
• Propagation Delay Time: 0.47 ns at 3 V to 5.5 V
• Supply Voltage (max): - 5.5 V, + 5.5 V
• Supply Voltage (min): - 3 V, + 3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Input Lines: 4.0
• Number Of Output Lines: 2.0
• Logical Function: Mux
• Configuration: 1 x 4:1/2 x 2:1
• Number Of Inputs: 4
• Number Of Outputs: 2
• Operating Supply Voltage (typ): -3.3/-5/3.3/5V
• Operating Supply Voltage (min): -3/3V
• Operating Supply Voltage (max): -5.5/5.5V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Package Type: QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output High, Low: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 1. 20−Lead Package (Top View) and Logic Diagram
Warning: All V
to Power Supply to guarantee proper operation.
V
D0a
20
CC
1
1
D0a
Q0
19
2
V
CC
Q0
18
BBO
3
NOTE:
and V
0
SEL0
D0b
17
4
EE
The Exposed Pad (EP) on package bottom must be attached to a heat−sinking conduit.
The Exposed Pad may only be electrically connected to V
pins must be externally connected
D0b
16
5
V
D0b
D0b
D1a
D1a
SEL1
BB0
D1a
15
6
1
D1a
V
1
2
3
4
5
14
7
CC
Figure 1. QFN−20 Pinout
V
Q1
D0a
13
BB1
8
V
20
6
BB1
0
http://onsemi.com
Q1
D1b
12
D1b
9
D0a
MC10/100EP56
19
7
V
D1b
10
V
D1b
11
EE
18
CC
2
8
V
Q0
17
EE
9
(Top View)
Q0
16
10
Q1
* Pins will default LOW when left open.
Table 1. PIN DESCRIPTION
Table 2. TRUTH TABLE
PIN
D0a* − D1a*
D0a* − D1a*
D0b* − D1b*
D0b* − D1b*
SEL0* − SEL1*
COM_SEL*
V
Q0 − Q1
Q0 − Q1
V
V
EP
SEL0
BB0
CC
EE
X
H
H
L
L
EE
.
, V
15
14
13
12
11
BB1
SEL1
SEL1
X
H
H
L
L
Exposed Pad
SEL0
COM_SEL
V
Q1
CC
COM_SEL
ECL Common Select Input
FUNCTION
ECL Input Data a
ECL Input Data a Invert
ECL Input Data b
ECL Input Data b Invert
ECL Indiv. Select Input
Output Reference Voltage
ECL True Outputs
ECL Inverted Outputs
Positive Supply
Negative Supply
Exposed Pad
H
L
L
L
L
Q0,
Q0
a
b
b
a
a
Q1,
Q1
a
b
a
a
b