DS2153QN-A7 Maxim Integrated, DS2153QN-A7 Datasheet - Page 29
DS2153QN-A7
Manufacturer Part Number
DS2153QN-A7
Description
In Stock
Manufacturer
Maxim Integrated
Datasheet
1.DS2153QA7.pdf
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DS2153Q
7 Sa DATA LINK CONTROL AND OPERATION
The DS2153Q provides for access to the proposed E1 performance monitor data link in the Sa bit
positions. The device allows access to the Sa bits either via a set of two internal registers (RNAF and
TNAF) or via two external pins (RLINK and TLINK).
On the receive side, the Sa bits are always reported in the internal RNAF register (see Section
12
for more
details). All five Sa bits are always output at the RLINK pin. See Section
14
for detailed timing. Via
RCR2, the user can control the RLCLK pin to pulse during any combination of Sa bits. This allows the
user to create a clock that can be used to capture the needed Sa bits.
On the transmit side, the individual Sa bits can be either sourced from the internal TNAF register
(TCR1.6 = 0) or from the external TLINK pin. Via TCR2, the DS2153Q can be programmed to source
any combination of the additional bits from the TLINK pin. If the user wishes to pass the Sa bits through
the DS2153Q without them being altered, then the device should be set up to source all five Sa bits via
the TLINK pin and the TLINK pin should be tied to the TSER pin. See the timing diagrams and the
transmit data flow diagram in Section
14
for examples.
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