DS2153QN-A7 Maxim Integrated, DS2153QN-A7 Datasheet - Page 46

Manufacturer Part Number

DS2153QN-A7

Description

In Stock

Manufacturer

Maxim Integrated

Datasheet

1.DS2153QA7.pdf (60 pages)

14 TIMING DIAGRAMS

Figure 14-1. Receive Side Timing

Figure 14-2. Receive Side Boundary Timing (with Elastic Stores Disabled)

NOTE 1: RSYNC IN THE FRAME MODE (RCR1.6 = 0).

NOTE 2: RSYNC IN THE MULTIFRAME MODE (RCR1.6 = 1).

NOTE 3: RLCLK IS PROGRAMMED TO OUTPUT JUST THE Sa4 BIT.

NOTE 4: RLINK WILL ALWAYS OUTPUT ALL FIVE Sa BITS AS WELL AS THE REST OF THE RECEIVE DATA STREAM.

NOTE 5: THIS DIAGRAM ASSUMES THE CAS MF BEGINS WITH THE FAS WORD.

NOTE 1: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 2.

NOTE 2: RLINK IS PROGRAMMED TO OUTPUT THE Sa4 BITS.

NOTE 3: RLINK IS PROGRAMMED TO OUTPUT THE Sa4 AND Sa8 BITS.

NOTE 4: RLINK IS PROGRAMMED TO OUTPUT THE Sa5 AND Sa7 BITS.

NOTE 5: SHOWN IS A NON-ALIGN FRAME BOUNDARY.

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