FM24C256-GTR Ramtron, FM24C256-GTR Datasheet - Page 2

• Manufacturer Part Number: FM24C256-GTR
• Description: fm24c256 series 256 k-bit (32k x 8) 5 v 3 us serial...
• Manufacturer: Ramtron

Pin Description
Rev 3.1
May 2005
A0-A2
Pin Name
A0-A2
WP
SDA
SCL
VDD
VSS
SCL
WP
SDA
Supply
Supply
Type
Input
Input
Input
`
I/O
Pin Description
Address 2-0: These pins are used to select one of up to 8 devices of the same type on
the same two-wire bus. To select the device, the address value on the three pins must
match the corresponding bits contained in the device address. The address pins are
pulled down internally.
Write Protect: When WP is high, the entire array will be write-protected. When WP is
low, all addresses may be written. This pin is internally pulled down.
Serial Data/Address: This is a bi-directional input used to shift serial data and
addresses for the two-wire interface. It employs an open-drain output and is intended
to be wire-OR’d with other devices on the two-wire bus. The input buffer incorporates
a Schmitt trigger for improved noise immunity and the output driver has slope control
for falling edges. An external pull-up resistor is required.
Serial Clock: The serial clock input for the two-wire interface. Data is clocked out of
the device on the SCL falling edge, and clocked in on the SCL rising edge. The SCL
input also incorporates a Schmitt trigger input for improved noise immunity.
Supply Voltage: 5V
Ground
Serial to Parallel
Counter
Control Logic
Converter
Figure 1. Block Diagram
Address
Latch
FRAM Array
Data Latch
4,096 x 64
8
FM24C256
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