5V9351PFGI IDT, 5V9351PFGI Datasheet
5V9351PFGI
Specifications of 5V9351PFGI
Related parts for 5V9351PFGI
5V9351PFGI Summary of contents
Page 1
... CMOS clock driver input. If PLL_EN is set to low and REF_SEL to high, it will bypass the PLL. By doing so, the IDT5V9351 will be in clock buffer mode. Any clock applied to TCLK will be divided down to four output banks. When PLL_EN is set high, PLL is enabled. Any clock applied to TCLK will be clocked in both phase and frequency to FBIN ...
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... GND 8 PECL_CLK TQFP TOP VIEW LOGIC DIAGRAM (1, NOTES: 1. IDT5V9351 requires an external RC filter for the analog power supply pin V 2. For V = 2.5V 9-10Ω 22μ For V = 3.3V 5-15Ω 22μ ABSOLUTE MAXIMUM RATINGS Symbol V CC ...
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... IDT5V9351 LOW VOLTAGE PLL CLOCK DRIVER PIN DESCRIPTION Terminal Name No. Type Description PECL-CLK Differential clock reference, LOW voltage positive ECL input PECL-CLK TCLK 30 I Single-ended reference clock signal or test clock FBIN 2 I Feedback signal input REF_SEL 32 I Reference clock input ...
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... CC I Maximum PLL Supply Current CCPLL NOTES (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V CMR (DC) specification. 2. The IDT5V9351 outputs can drive series or paralell terminated 50Ω (or 50Ω SELC SELD ...
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... Maximum Output Frequency MAX t Propagation Delay (Static Phase Offset Output Disable Time PLZ PHZ Output Enable Time PZL PZH B PLL Closed Loop Bandwidth W ÷ t Cycle-to-Cycle Jitter 4 feedback J (Single Output Frequency Configuration) ÷ Period Jitter 4 feedback JIT PER (Single Output Frequency Configuration) t (φ ...
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... Normal operation is obtained when the HIGH input is within the V CMR lies within the V specification The IDT5V9351 outputs can drive series or paralell terminated 50Ω (or 50Ω PLL INPUT REFERENCE CHARACTERISTICS V = 2.5V ± 5 -40°C to +85°C ...
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... Maximum Output Frequency MAX t Input to FBIN Delay Output Disable Time PLZ PHZ Output Enable Time PZL PZH B PLL Closed Loop Bandwidth W ÷ t Cycle-to-Cycle Jitter 4 feedback J (Single Output Frequency Configuration) ÷ Period Jitter 4 feedback JIT PER (Single Output Frequency Configuration) t (φ ...
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... Input Characteristics for 2.5V 1. 0.6V Output Output Test Conditions for V IDT5V9351 D.U. 50Ω 50Ω TCLK AC Test Reference for V = 2.5V and V CC IDT5V9351 D.U. 50Ω 50Ω PECL_CLK AC Test Reference 0. CLK FBIN V CC 1.7V PECL_CLK 0.7V PECL_CLK ...
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... IDT5V9351 LOW VOLTAGE PLL CLOCK DRIVER CCLK FBIN I/O Jitter 100 Output Duty Cycle Tn+1 Tn Cycle-to-Cycle Jitter T 0 Period Jitter 9 INDUSTRIAL TEMPERATURE RANGE J( MEAN GND Tn 1/f J(PER) 0 ...
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... CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 X Process -40°C to +85°C (Industriall) I Thin Quad Flat Pack PF TQFP - Green PFG 5V9351 Low Voltage PLL Clock Driver for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 10 INDUSTRIAL TEMPERATURE RANGE for Tech Support: clockhelp@idt.com ...