5V9351PFGI IDT, 5V9351PFGI Datasheet - Page 7

• Manufacturer Part Number: 5V9351PFGI
• Description: Clock Drivers & Distribution 4 Bank PLL Clock Dvr w/PECL Input
• Manufacturer: IDT

Specifications of 5V9351PFGI

• Rohs: yes
• Part # Aliases: IDT5V9351PFGI

NOTES:
1. AC Characteristics apply for parallel output termination of 50Ω to V
2. V
AC ELECTRICAL CHARACTERISTICS
T
IDT5V9351
LOW VOLTAGE PLL CLOCK DRIVER
A
specifications.
Symbol
t
t
t
PLZ
PZL
= -40°C to +85°C, V
JIT
CMR
t
V
t
JIT
t
t
SK
V
f
f
LOCK
R
B
t
VCO
MAX
t
CMR
PW
PD
(
, t
, t
t
, t
PP
J
(
W
PER
(φ)
(
O
PHZ
PZH
AC
F
)
) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
)
Parameter
Output Rise/Fall Time
Peak-to-Peak Input Voltage
Common Mode Range
Output Duty Cycle
Output to Output Skew
PLL VCO Lock Range
Maximum Output Frequency
Input to FBIN Delay
Output Disable Time
Output Enable Time
PLL Closed Loop Bandwidth
Cycle-to-Cycle Jitter
(Single Output Frequency Configuration)
Period Jitter
(Single Output Frequency Configuration)
I/O Phase Jitter
Maximum PLL Lock Time
CC
÷
= 2.5V ± 5%
4 feedback
÷
(2)
4 feedback
TT
÷
÷
÷
.
2 feedback
4 feedback
8 feedback
Conditions
0.6V to 1.8V
LVPECL
LVPECL
100-200 MHz
50-100 MHz
25-50 MHz
÷
÷
÷
TCLK to FBIN
PECL_CLK to FBIN
RMS Value
RMS Value
RMS Value
2 output
4 output
8 output
(1)
7
PLL to transfer
characteristic
-3db point of
48.75
Min.
47.5
-100
500
200
100
0.1
1.2
45
—
50
25
—
—
—
—
—
—
—
—
—
0
INDUSTRIAL TEMPERATURE RANGE
CMR
range and the input swing lies within V
0.7 - 2
4 - 15
6 - 25
Typ.
2 - 7
—
—
—
50
50
50
—
—
—
—
—
—
—
—
—
10
—
8
V
CC
51.75
1000
Max
52.5
150
400
200
100
100
300
55
50
12
12
—
—
—
22
15
—
1
1
- 0.6
MHz
MHz
MHz
Unit
mV
ms
ns
%
ps
ps
ns
ns
ps
ps
ps
V
PP
(
AC
)