533BB000491DG Silicon Labs, 533BB000491DG Datasheet - Page 4

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533BB000491DG

Manufacturer Part Number
533BB000491DG
Description
Standard Clock Oscillators DUAL XO 6 PIN 0.3PS RS JTR
Manufacturer
Silicon Labs
Series
Si533r
Datasheet

Specifications of 533BB000491DG

Product Category
Standard Clock Oscillators
Rohs
yes
Product
XO
Frequency
491 MHz
Frequency Stability
20 PPm
Supply Voltage
2.97 V to 3.63 V
Termination Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Maximum Operating Temperature
+ 85 C
Output Format
LVDS
Dimensions
5 mm W x 7 mm L
Supply Voltage - Max
3.63 V
Supply Voltage - Min
2.97 V
S i 533
Table 4. CLK± Output Phase Jitter
Table 5. CLK± Output Period Jitter
Table 6. CLK± Output Phase Noise (Typical)
4
Phase Jitter (RMS)
for F
Phase Jitter (RMS)
for F
Phase Jitter (RMS)
for F
CMOS Output Only
Notes:
Period Jitter*
*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.
1. Refer to AN256 for further information.
2. Max offset frequencies: 80 MHz for FOUT > 250 MHz, 20 MHz for 50 MHz < FOUT <250 MHz,
OUT
OUT
OUT
2 MHz for 10 MHz < FOUT <50 MHz.
> 500 MHz
of 125 to 500 MHz
of 10 to 160 MHz
Offset Frequency (f)
Parameter
Parameter
100 MHz
100 kHz
10 MHz
100 Hz
10 kHz
1 MHz
1 kHz
1
1
Symbol
Symbol
J
PER
J
J
J
120.00 MHz
50 kHz to 80 MHz (OC-192)
50 kHz to 80 MHz (OC-192)
12 kHz to 20 MHz (OC-48)
12 kHz to 20 MHz (OC-48)
12 kHz to 20 MHz (OC-48)
LVDS
–112
–122
–132
–137
–144
–150
n/a
50 kHz to 20 MHz
Test Condition
Test Condition
Rev. 1.2
Peak-to-Peak
RMS
156.25 MHz
LVPECL
2
–105
–122
–128
–135
–144
–147
n/a
2
2
Min
Min
622.08 MHz
LVPECL
0.25
0.26
0.36
0.34
0.62
0.61
Typ
Typ
–107
–116
–121
–134
–146
–148
–97
14
2
Max
0.40
0.37
0.50
0.42
Max
dBc/Hz
Units
Units
Units
ps
ps
ps
ps
ps
ps
ps
ps

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