C8051F330DK Silicon Laboratories Inc, C8051F330DK Datasheet

DEV KIT FOR C8051F330/F331

C8051F330DK

Manufacturer Part Number
C8051F330DK
Description
DEV KIT FOR C8051F330/F331
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets

Specifications of C8051F330DK

Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F33x
Interface Type
RS-232
Operating Supply Voltage
7 V to 15 V
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F330
Silicon Family Name
C8051F33x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
Silicon Laboratories C8051F330, C8051F331
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1264
Rev. 1.7 12/10
Analog Peripherals
-
-
-
On-Chip Debug
-
-
-
-
Supply Voltage 2.7 to 3.6 V
-
-
Temperature Range: –40 to +85 °C
10-Bit ADC (‘F330/2/4 only)
10-Bit Current Output DAC (‘F330 only)
Comparator
On-chip debug circuitry facilitates full speed, non-
intrusive in-system debug (no emulator required)
Provides breakpoints, single stepping, 
inspect/modify memory and registers
Superior performance to emulation systems using
ICE-chips, target pods, and sockets
Low cost, complete development kit
Typical operating current: 6.4 mA at 25 MHz;
Typical stop mode current: 0.1 µA
Up to 200 ksps
Up to 16 external single-ended or differential inputs
VREF from internal VREF, external pin or V
Internal or external start of conversion source
Built-in temperature sensor
Programmable hysteresis and response time
Configurable as interrupt or reset source
Low current (0.4 µA)
INTERRUPTS
SENSOR
M
A
U
X
INTERNAL OSCILLATOR
TEMP
ISP FLASH
FLEXIBLE
9 µA at 32 kHz
24.5 MHz PRECISION
‘F330/2/4 only
2/4/8 kB
PERIPHERALS
200 ksps
HIGH-SPEED CONTROLLER CORE
Copyright © 2010 by Silicon Laboratories
ANALOG
10-bit
ADC
DD
COMPARATOR
‘F330 only
VOLTAGE
Current
+
-
CIRCUITRY
10-bit
8051 CPU
(25 MIPS)
DAC
DEBUG
LOW FREQUENCY INTERNAL
High Speed 8051 µC Core
-
-
-
Memory
-
-
Digital Peripherals
-
-
-
-
-
Clock Sources
-
-
-
20-Pin QFN Package
Timer 0
Timer 1
Timer 2
Timer 3
SMBus
UART
Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
Up to 25 MIPS throughput with 25 MHz clock
Expanded interrupt handler
768 bytes internal data RAM (256 + 512)
8 kB (‘F330/1), 4 kB (‘F332/3), or 2 kB (‘F334/5)
Flash; In-system programmable in 512-byte Sec-
tors—512 bytes are reserved in the 8 kB devices
17 Port I/O; All 5 V tolerant with high sink current
Hardware enhanced UART, SMBus™, and
enhanced SPI™ serial ports
Four general purpose 16-bit counter/timers
16-Bit programmable counter array (PCA) with three
capture/compare modules
Real time clock mode using PCA or timer and exter-
nal clock source
Two internal oscillators:
External oscillator: Crystal, RC, C, or clock 
(1 or 2 pin modes)
Can switch between clock sources on-the-fly; useful
in power saving modes
PCA
SPI
DIGITAL I/O
OSCILLATOR
24.5 MHz with ±2% accuracy supports crystal-less
UART operation
80/40/20/10 kHz low frequency, low power
C8051F330/1/2/3/4/5
768 B SRAM
POR
Mixed-Signal ISP Flash MCU
Port 0
Port 1
P2.0
WDT
C8051F330/1/2/3/4/5

C8051F330DK Summary of contents

Page 1

Analog Peripherals - 10-Bit ADC (‘F330/2/4 only) • 200 ksps • external single-ended or differential inputs • VREF from internal VREF, external pin or V • Internal or external start of conversion source • Built-in ...

Page 2

C8051F330/1/2/3/4/5 2 Rev. 1.7 ...

Page 3

Table of Contents 1. System Overview.................................................................................................... 17 1.1. CIP-51™ Microcontroller Core.......................................................................... 22 1.1.1. Fully 8051 Compatible.............................................................................. 22 1.1.2. Improved Throughput ............................................................................... 22 1.1.3. Additional Features .................................................................................. 23 1.2. On-Chip Memory............................................................................................... 24 1.3. On-Chip Debug Circuitry................................................................................... 25 1.4. Programmable Digital I/O ...

Page 4

C8051F330/1/2/3/4/5 9.2.5. Stack ....................................................................................................... 78 9.2.6. Special Function Registers....................................................................... 79 9.2.7. Register Descriptions ............................................................................... 83 9.3. Interrupt Handler ............................................................................................... 85 9.3.1. MCU Interrupt Sources and Vectors ........................................................ 86 9.3.2. External Interrupts .................................................................................... 87 9.3.3. Interrupt Priorities ..................................................................................... 87 9.3.4. Interrupt ...

Page 5

Purpose Port I/O ............................................................................... 129 15. SMBus ................................................................................................................... 135 15.1.Supporting Documents ................................................................................... 136 15.2.SMBus Configuration...................................................................................... 136 15.3.SMBus Operation ........................................................................................... 136 15.3.1.Arbitration............................................................................................... 137 15.3.2.Clock Low Extension.............................................................................. 138 15.3.3.SCL Low Timeout................................................................................... 138 15.3.4.SCL High (SMBus Free) Timeout .......................................................... 138 15.4.Using the ...

Page 6

C8051F330/1/2/3/4/5 18.2.2.8-bit Timers with Auto-Reload................................................................ 186 18.3.Timer 3 .......................................................................................................... 189 18.3.1.16-bit Timer with Auto-Reload................................................................ 189 18.3.2.8-bit Timers with Auto-Reload................................................................ 190 19. Programmable Counter Array ............................................................................. 193 19.1.PCA Counter/Timer ........................................................................................ 194 19.2.Capture/Compare Modules ............................................................................ 195 19.2.1.Edge-triggered Capture Mode................................................................ 196 19.2.2.Software Timer ...

Page 7

List of Figures 1. System Overview Figure 1.1. C8051F330 Block Diagram.................................................................... 19 Figure 1.2. C8051F331 Block Diagram.................................................................... 19 Figure 1.3. C8051F332 Block Diagram.................................................................... 20 Figure 1.4. C8051F333 Block Diagram.................................................................... 20 Figure 1.5. C8051F334 Block Diagram.................................................................... 21 Figure 1.6. C8051F335 Block ...

Page 8

C8051F330/1/2/3/4/5 Figure 10.2. Power-On and VDD Monitor Reset Timing .......................................... 98 11. Flash Memory Figure 11.1. Flash Program Memory Map.............................................................. 105 12. External RAM 13. Oscillators Figure 13.1. Oscillator Diagram.............................................................................. 113 Figure 13.2. External 32.768 kHz Quartz Crystal Oscillator Connection ...

Page 9

Figure 18.3. T0 Mode 3 Block Diagram.................................................................. 180 Figure 18.4. Timer 2 16-Bit Mode Block Diagram .................................................. 185 Figure 18.5. Timer 2 8-Bit Mode Block Diagram .................................................... 186 Figure 18.6. Timer 3 16-Bit Mode Block Diagram .................................................. 189 Figure 18.7. ...

Page 10

List of Tables 1. System Overview Table 1.1. Product Selection Guide ......................................................................... 18 2. Absolute Maximum Ratings Table 2.1. Absolute Maximum Ratings .................................................................... 31 3. Global Electrical Characteristics Table 3.1. Global Electrical Characteristics ............................................................. 32 Table 3.2. Index to Electrical ...

Page 11

C8051F330/1/2/3/4/5 Table 16.2. Timer Settings for Standard Baud Rates Using an  External 25.0 MHz Oscillator .............................................................. 160 Table 16.3. Timer Settings for Standard Baud Rates Using an  External 22.1184 MHz Oscillator ........................................................ 161 Table 16.4. Timer Settings for ...

Page 12

List of Registers SFR Definition 5.1. AMX0P: AMUX0 Positive Channel Select . . . . . . . . . . . . . . . . . . . 47 SFR Definition 5.2. AMX0N: AMUX0 Negative Channel Select . ...

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C8051F330/1/2/3/4/5 SFR Definition 14.4. P0MDIN: Port0 Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 SFR Definition 14.5. ...

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C2 Register Definition 20.4. FPCTL: C2 Flash Programming Control . . . . . . . . . . . . 210 C2 Register Definition 20.5. FPDAT: C2 Flash Programming Data . . . . . . . . . ...

Page 15

System Overview C8051F330/1/2/3/4/5 devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted fea- tures are listed below. Refer to Table 1.1 for specific product feature selection. • High-speed pipelined 8051-compatible microcontroller core ( MIPS) • In-system, full-speed, non-intrusive ...

Page 16

C8051F330/1/2/3/4/5 Table 1.1. Product Selection Guide  C8051F330- 768  C8051F331- 768  C8051F332- 768  C8051F333- 768  C8051F334- 768  C8051F335- 768 18    ...

Page 17

Analog/Digital VDD Power GND C2D Debug HW Reset RST/C2CK Brown- POR Out External XTAL1 Oscillator XTAL2 Circuit System Clock 24.5 MHz (2%) Internal Oscillator 80 kHz Internal Oscillator Figure 1.1. C8051F330 Block Diagram Analog/Digital VDD Power GND C2D Debug HW ...

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C8051F330/1/2/3/4/5 Analog/Digital VDD Power GND C2D Debug HW Reset /RST/C2CK Brown- POR Out External XTAL1 Oscillator XTAL2 Circuit System Clock 24.5 MHz (2%) Internal Oscillator 80 kHz Internal Oscillator Figure 1.3. C8051F332 Block Diagram Analog/Digital VDD Power GND C2D Debug ...

Page 19

Analog/Digital VDD Power GND C2D Debug HW Reset /RST/C2CK Brown- POR Out External XTAL1 Oscillator XTAL2 Circuit System Clock 24.5 MHz (2%) Internal Oscillator 80 kHz Internal Oscillator Figure 1.5. C8051F334 Block Diagram Analog/Digital VDD Power GND C2D Debug HW ...

Page 20

C8051F330/1/2/3/4/5 1.1. CIP-51™ Microcontroller Core 1.1.1. Fully 8051 Compatible The C8051F330/1/2/3/4/5 family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. ...

Page 21

Additional Features The C8051F330/1/2/3/4/5 SoC family includes several key enhancements to the CIP-51 core and periph- erals to improve performance and ease of use in end applications. The extended interrupt handler provides 14 interrupt sources into the CIP-51 (as ...

Page 22

C8051F330/1/2/3/4/5 1.2. On-Chip Memory The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general purpose RAM, and ...

Page 23

... All the peripherals (except for the ADC and SMBus) are stalled when the MCU is halted, during single stepping breakpoint in order to keep them synchronized. The C8051F330DK development kit provides all the hardware and software necessary to develop applica- tion code and perform in-circuit debugging with the C8051F330/1/2/3/4/5 MCUs. The kit includes software with a developer's studio and debugger, an integrated 8051 assembler, and a debug adapter ...

Page 24

C8051F330/1/2/3/4/5 1.4. Programmable Digital I/O and Crossbar C8051F330/1/2/3/4/5 devices include 17 I/O pins (two byte-wide Ports and one 1-bit-wide Port). The C8051F330/1/2/3/4/5 Ports behave like typical 8051 Ports with a few enhancements. Each Port pin may be configured as an ...

Page 25

Programmable Counter Array An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the four 16-bit general pur- pose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with three program- mable capture/compare modules. The PCA ...

Page 26

C8051F330/1/2/3/4/5 1.7. 10-Bit Analog to Digital Converter The C8051F330/2/4 devices include an on-chip 10-bit SAR ADC with a 16-channel differential input multi- plexer. With a maximum throughput of 200 ksps, the ADC offers true 10-bit linearity with an INL and ...

Page 27

Comparators C8051F330/1/2/3/4/5 devices include an on-chip voltage comparator that is enabled/disabled and config- ured via user software. Port I/O pins may be configured as comparator inputs via a selection mux. Two comparator outputs may be routed to a Port ...

Page 28

C8051F330/1/2/3/4/5 1.9. 10-bit Current Output DAC The C8051F330 device includes a 10-bit current-mode Digital-to-Analog Converter (IDA0). The maximum current output of the IDA0 can be adjusted for three different current settings; 0.5 mA, 1 mA, and 2 mA. IDA0 features ...

Page 29

Absolute Maximum Ratings Table 2.1. Absolute Maximum Ratings Parameter Ambient temperature under bias Storage Temperature Voltage on any Port I/O Pin or RST with respect to GND Voltage on V with respect to GND DD Maximum Total current through ...

Page 30

C8051F330/1/2/3/4/5 3. Global Electrical Characteristics Table 3.1. Global Electrical Characteristics –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter Digital Supply Voltage Digital Supply RAM Data Retention Voltage SYSCLK (System Clock) (Note 2) T (SYSCLK High Time) ...

Page 31

Table 3.1. Global Electrical Characteristics –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter Digital Supply Current—CPU Inactive (Idle Mode, not fetching instructions from Flash) I (Note ...

Page 32

C8051F330/1/2/3/4/5 Table 3.2. Index to Electrical Characteristics Tables Peripheral Electrical Characteristics ADC0 Electrical Characteristics IDAC Electrical Characteristics Voltage Reference Electrical Characteristics Comparator Electrical Characteristics Reset Electrical Characteristics Flash Electrical Characteristics Internal Oscillator Electrical Characteristics Port I/O DC Electrical Characteristics 34 ...

Page 33

Pinout and Package Definitions Table 4.1. Pin Definitions for the C8051F330/1/2/3/4/5 Pin Pin Name ‘F330/1/2/ ’F330-GP 3/4/5- GND 2 5 RST C2CK P2. C2D P0. VREF P0 ...

Page 34

C8051F330/1/2/3/4/5 Table 4.1. Pin Definitions for the C8051F330/1/2/3/4/5 (Continued) Pin Pin Name ‘F330/1/2/ ’F330-GP 3/4/5-GM P0. CNVSTR ...

Page 35

P0.0 1 GND 2 C8051F330/1/2/3/4/5-GM VDD 3 /RST/C2CK 4 P2.0/C2D 5 Figure 4.1. QFN-20 Pinout Diagram (Top View) C8051F330/1/2/3/4/5 Top View GND Rev. 1.7 15 P0.6 14 P0.7 13 P1.0 12 P1.1 11 P1.2 37 ...

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C8051F330/1/2/3/4/5 Figure 4.2. QFN-20 Package Drawing Table 4.2. QFN-20 Package Dimensions Dimension Min Typ A 0.80 0.90 A1 0.00 0.02 b 0.18 0.23 D 4.00 BSC. D2 2.00 2.15 e 0.50 BSC. E 4.00 BSC. E2 2.00 2.15 Notes: 1. ...

Page 37

Figure 4.3. QFN-20 Recommended PCB Land Pattern Table 4.3. QFN-20 PCB Land Pattern Dimesions Dimension Min Max C1 3.70 C2 3.70 E 0.50 X1 0.20 0.30 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. ...

Page 38

ADC (ADC0, C8051F330/2/4 only) The ADC0 subsystem for the C8051F330/2/4 consists of two analog multiplexers (referred to collectively as AMUX0) with 16 total input selections, and a 200 ksps, 10-bit successive-approximation-register ADC with integrated track-and-hold and programmable window ...

Page 39

C8051F330/1/2/3/4/5 measured from ‘0’ to VREF x 1023/1024. Example codes are shown below for both right-justified and left- justified data. Unused bits in the ADC0H and ADC0L registers are set to ‘0’. Input Voltage Right-Justified ADC0H:ADC0L VREF x 1023/1024 VREF ...

Page 40

Figure 5.2. Typical Temperature Sensor Transfer Function 5.3. Modes of Operation ADC0 has a maximum conversion speed of 200 ksps. The ADC0 conversion clock is a divided version of the system clock, ...

Page 41

C8051F330/1/2/3/4/5 5.3.1. Starting a Conversion A conversion can be initiated in one of six ways, depending on the programmed states of the ADC0 Start of Conversion Mode bits (AD0CM2–0) in register ADC0CN. Conversions may be initiated by one of the ...

Page 42

Tracking Modes Each ADC0 conversion must be preceded by a minimum tracking time in order for the converted result to be accurate. The minimum tracking time is given in Table 5.1. The AD0TM bit in register ADC0CN controls the ...

Page 43

C8051F330/1/2/3/4/5 5.3.3. Settling Time Requirements When the ADC0 input configuration is changed (i.e., a different AMUX0 selection is made), a minimum tracking time is required before an accurate conversion can be performed. This tracking time is determined by the AMUX0 ...

Page 44

SFR Definition 5.1. AMX0P: AMUX0 Positive Channel Select AMX0P4 Bit7 Bit6 Bit5 Bits7–5: UNUSED. Read = 000b; Write = don’t care. Bits4–0: AMX0P4–0: AMUX0 Positive Input Selection AMX0P4–0 00000 00001 00010 00011 00100 00101 ...

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C8051F330/1/2/3/4/5 SFR Definition 5.2. AMX0N: AMUX0 Negative Channel Select Bit7 Bit6 Bit5 Bits7–5: UNUSED. Read = 000b; Write = don’t care. Bits4–0: AMX0N4–0: AMUX0 Negative Input Selection. Note that when GND is selected as ...

Page 46

SFR Definition 5.3. ADC0CF: ADC0 Configuration R/W R/W R/W AD0SC4 AD0SC3 AD0SC2 AD0SC1 Bit7 Bit6 Bit5 Bits7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from system clock by the following equation, where AD0SC refers to ...

Page 47

C8051F330/1/2/3/4/5 SFR Definition 5.6. ADC0CN: ADC0 Control R/W R/W R/W AD0EN AD0TM AD0INT AD0BUSY AD0WINT AD0CM2 AD0CM1 AD0CM0 00000000 Bit7 Bit6 Bit5 Bit7: AD0EN: ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. 1: ADC0 Enabled. ADC0 is ...

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Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-pro- grammed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system, saving code space ...

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C8051F330/1/2/3/4/5 SFR Definition 5.9. ADC0LTH: ADC0 Less-Than Data High Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: High byte of ADC0 Less-Than Data Word SFR Definition 5.10. ADC0LTL: ADC0 Less-Than Data Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: ...

Page 50

Window Detector In Single-Ended Mode Figure 5.5 shows two example window comparisons for right-justified, single-ended data, with ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). In single-ended mode, the input voltage can range from ‘0’ to VREF x ...

Page 51

C8051F330/1/2/3/4/5 5.4.2. Window Detector In Differential Mode Figure 5.7 shows two example window comparisons for right-justified, differential data, with ADC0LTH:ADC0LTL = 0x0040 (+64d) and ADC0GTH:ADC0GTH = 0xFFFF (–1d). In differential mode, the measurable voltage between the input pins is between ...

Page 52

Table 5.1. ADC0 Electrical Characteristics V = 3.0 V, VREF = 2.40 V (REFSL=0), DD Parameter Resolution Integral Nonlinearity Differential Nonlinearity Guaranteed Monotonic Offset Error Full Scale Error Offset Temperature Coefficient Dynamic performance (10 kHz sine-wave single-ended input ...

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C8051F330/1/2/3/4/5 56 Rev. 1.7 ...

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Current Mode DAC (IDA0, C8051F330 only) The C8051F330 device includes a 10-bit current-mode Digital-to-Analog Converter (IDAC). The maximum current output of the IDAC can be adjusted for three different current settings; 0.5 mA, 1 mA, and 2 mA. ...

Page 55

C8051F330/1/2/3/4/5 6.1.2. Update Output Based on Timer Overflow Similar to the ADC operation, in which an ADC conversion can be initiated by a timer overflow indepen- dently of the processor, the IDAC outputs can use a Timer overflow to schedule ...

Page 56

SFR Definition 6.1. IDA0CN: IDA0 Control R/W R/W R/W IDA0EN IDA0CM Bit7 Bit6 Bit5 Bit 7: IDA0EN: IDA0 Enable. 0: IDA0 Disabled. 1: IDA0 Enabled. Bits 6–4: IDA0CM[2:0]: IDA0 Update Source Select bits. 000: DAC output updates on Timer 0 ...

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C8051F330/1/2/3/4/5 SFR Definition 6.3. IDA0L: IDA0 Data Word LSB R/W R/W R — Bit7 Bit6 Bit5 Bits 7–6: IDA0 Data Word Low-Order Bits. Lower 2 bits of the 10-bit Data Word. Bits 5–0: UNUSED. Read = 000000b, Write = don’t ...

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Voltage Reference (C8051F330/2/4 only) The Voltage reference MUX on the C8051F330/2/4 devices is configurable to use an externally connected voltage reference, the internal reference voltage generator, or the V Figure 7.1). The REFSL bit in the Reference Control register ...

Page 59

C8051F330/1/2/3/4/5 SFR Definition 7.1. REF0CN: Reference Control Bit7 Bit6 Bit5 Bits7–4: UNUSED. Read = 0000b; Write = don’t care. Bit3: REFSL: Voltage Reference Select. This bit selects the source for the internal voltage reference. ...

Page 60

Table 7.1. Voltage Reference Electrical Characteristics V = 3.0 V; –40 to +85 °C unless otherwise specified. DD Parameter Output Voltage 25 °C ambient VREF Short-Circuit Current VREF Temperature  Coefficient Load Regulation Load = 0 to 200 µA to ...

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C8051F330/1/2/3/4/5 64 Rev. 1.7 ...

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Comparator0 C8051F330/1/2/3/4/5 devices include an on-chip programmable voltage comparator, Comparator0, shown in Figure 8.1. The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two outputs that are optionally available at the Port pins: a synchronous ...

Page 63

C8051F330/1/2/3/4/5 The Comparator output can be polled in software, used as an interrupt source, and/or routed to a Port pin. When routed to a Port pin, the Comparator output is available asynchronous or synchronous to the system clock; the asynchronous ...

Page 64

Comparator falling-edge occurrence, and the CP0RIF flag is set to logic 1 upon the Com- parator rising-edge occurrence. Once set, these bits remain set until cleared by software. The Comparator rising-edge interrupt mask is enabled by ...

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C8051F330/1/2/3/4/5 SFR Definition 8.2. CPT0MX: Comparator0 MUX Selection R/W R/W R/W CMX0N3 CMX0N2 CMX0N1 CMX0N0 CMX0P3 CMX0P2 CMX0P1 CMX0P0 Bit7 Bit6 Bit5 Bits7–4: CMX0N3–CMX0N0: Comparator0 Negative Input MUX Select. These bits select which Port pin is used as the Comparator0 ...

Page 66

SFR Definition 8.3. CPT0MD: Comparator0 Mode Selection CP0RIE CP0FIE Bit7 Bit6 Bit5 Bits7–6: UNUSED. Read = 00b, Write = don’t care. Bit5: CP0RIE: Comparator0 Rising-Edge Interrupt Enable. 0: Comparator0 Rising-edge interrupt disabled. 1: Comparator0 Rising-edge ...

Page 67

C8051F330/1/2/3/4/5 Table 8.1. Comparator Electrical Characteristics V = 3.0 V, –40 to +85 °C unless otherwise noted. DD Parameter CP0+ – CP0– = 100 mV Response Time: * Mode 0, Vcm = 1.5 V CP0+ – CP0– = –100 mV ...

Page 68

CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft- ware. The MCU family has a superset ...

Page 69

C8051F330/1/2/3/4/5 With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execu- tion ...

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Refer to for further details. Table 9.1. CIP-51 Instruction Set Summary Mnemonic ADD A, Rn Add register to A ADD A, direct Add direct byte to A ADD A, @Ri Add indirect RAM ...

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C8051F330/1/2/3/4/5 Table 9.1. CIP-51 Instruction Set Summary (Continued) Mnemonic XRL A, #data Exclusive-OR immediate to A XRL direct, A Exclusive- direct byte XRL direct, #data Exclusive-OR immediate to direct byte CLR A Clear A CPL A Complement A ...

Page 72

Table 9.1. CIP-51 Instruction Set Summary (Continued) Mnemonic CPL C Complement Carry CPL bit Complement direct bit ANL C, bit AND direct bit to Carry ANL C, /bit AND complement of direct bit to Carry ORL C, bit OR direct ...

Page 73

C8051F330/1/2/3/4/5 Notes on Registers, Operands and Addressing Modes Register R0–R7 of the currently selected register bank. @Ri - Data RAM location addressed indirectly through R0 or R1. rel - 8-bit, signed (two’s complement) offset relative to the first ...

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C8051F330/1 PROGRAM/DATA MEMORY (FLASH) RESERVED 0x1E00 0x1DFF 8 K FLASH (In-System Programmable in 512 Byte Sectors) 0x0000 C8051F332/3 PROGRAM/DATA MEMORY (FLASH) 0x0FFF 4 K FLASH (In-System Programmable in 512 Byte Sectors) 0x0000 C8051F334/5 PROGRAM/DATA MEMORY (FLASH) 0x7FF 2 K FLASH ...

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C8051F330/1/2/3/4/5 9.2.2. Data Memory The CIP-51 includes 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad mem- ory. ...

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Special Function Registers The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The CIP-51 duplicates the SFRs found in a ...

Page 77

C8051F330/1/2/3/4/5 Table 9.3. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address ACC 0xE0 Accumulator ADC0CF 0xBC ADC0 Configuration ADC0CN 0xE8 ADC0 Control ADC0GTH 0xC4 ADC0 Greater-Than Compare High ADC0GTL 0xC3 ADC0 ...

Page 78

Table 9.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address OSCXCN 0xB1 External Oscillator Control P0 0x80 Port 0 Latch P0MDIN 0xF1 Port 0 Input Mode Configuration P0MDOUT 0xA4 Port ...

Page 79

C8051F330/1/2/3/4/5 Table 9.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address SP 0x81 Stack Pointer SPI0CFG 0xA1 SPI Configuration SPI0CKR 0xA2 SPI Clock Rate Control SPI0CN 0xF8 SPI Control SPI0DAT ...

Page 80

Register Descriptions Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should not be set to logic l. Future product versions may use these bits to implement new features in which case ...

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C8051F330/1/2/3/4/5 SFR Definition 9.4. PSW: Program Status Word R/W R/W R Bit7 Bit6 Bit5 Bit7: CY: Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (addition borrow (subtraction). It ...

Page 82

SFR Definition 9.5. ACC: Accumulator R/W R/W R/W ACC.7 ACC.6 ACC.5 Bit7 Bit6 Bit5 Bits7–0: ACC: Accumulator. This register is the accumulator for arithmetic operations. SFR Definition 9. Register R/W R/W R/W B.7 B.6 B.5 Bit7 Bit6 Bit5 ...

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C8051F330/1/2/3/4 this is a dummy instruction with two-byte opcode. assembly: CLR EA ; clear EA bit. CLR EA ; this is a dummy instruction with two-byte opcode interrupt is posted during the ...

Page 84

External Interrupts The /INT0 and /INT1 external interrupt sources are configurable as active high or low, edge or level sensi- tive. The IN0PL (/INT0 Polarity) and IN1PL (/INT1 Polarity) bits in the IT01CF register select active high or active ...

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C8051F330/1/2/3/4/5 Table 9.4. Interrupt Summary Interrupt Interrupt Source Vector Reset 0x0000 External Interrupt 0 0x0003 (/INT0) Timer 0 Overflow 0x000B External Interrupt 1 0x0013 (/INT1) Timer 1 Overflow 0x001B UART0 0x0023 Timer 2 Overflow 0x002B SPI0 0x0033 SMB0 0x003B RESERVED ...

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Interrupt Register Descriptions The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the data sheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the ...

Page 87

C8051F330/1/2/3/4/5 SFR Definition 9.8. IP: Interrupt Priority R R/W R/W - PSPI0 PT2 Bit7 Bit6 Bit5 Bit7: UNUSED. Read = 1, Write = don't care. Bit6: PSPI0: Serial Peripheral Interface (SPI0) Interrupt Priority Control. This bit sets the priority of ...

Page 88

SFR Definition 9.9. EIE1: Extended Interrupt Enable 1 R/W R/W R/W ET3 Reserved ECP0 Bit7 Bit6 Bit5 Bit7: ET3: Enable Timer 3 Interrupt. This bit sets the masking of the Timer 3 interrupt. 0: Disable Timer 3 interrupts. 1: Enable ...

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C8051F330/1/2/3/4/5 SFR Definition 9.10. EIP1: Extended Interrupt Priority 1 R/W R/W R/W PT3 Reserved PCP0 Bit7 Bit6 Bit5 Bit7: PT3: Timer 3 Interrupt Priority Control. This bit sets the priority of the Timer 3 interrupt. 0: Timer 3 interrupts set ...

Page 90

SFR Definition 9.11. IT01CF: INT0/INT1 Configuration R/W R/W R/W IN1PL IN1SL2 IN1SL1 Bit7 Bit6 Bit5 *Note: Refer to SFR Definition 18.1 for INT0/1 edge- or level-sensitive interrupt selection. Bit7: IN1PL: /INT1 Polarity 0: /INT1 input is active low. 1: /INT1 ...

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C8051F330/1/2/3/4/5 9.4. Power Management Modes The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the CPU while leaving the peripherals and clocks active. In Stop mode, the CPU is halted, all inter- rupts ...

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Stop Mode Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruc- tion that sets the bit completes execution. In Stop mode the internal oscillator, CPU, and all digital peripher- ...

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C8051F330/1/2/3/4/5 96 Rev. 1.7 ...

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Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: • CIP-51 halts program execution • Special Function Registers (SFRs) are initialized to their ...

Page 95

C8051F330/1/2/3/4/5 10.1. Power-On Reset During power-up, the device is held in a reset state and the RST pin is driven low until delay occurs before the device is released from reset; the delay decreases as the ...

Page 96

Important Note: The V monitor must be enabled before it is selected as a reset source. Selecting the DD V monitor as a reset source before it is enabled and stabilized may cause a system reset. The proce- DD dure ...

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C8051F330/1/2/3/4/5 10.5. Comparator0 Reset Comparator0 can be configured as a reset source by writing a ‘1’ to the C0RSEF flag (RSTSRC.5). Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on chatter on ...

Page 98

SFR Definition 10.2. RSTSRC: Reset Source R R R/W - FERROR C0RSEF SWRSF Bit7 Bit6 Bit5 Note: Do not use read-modify-write operations (ORL, ANL) on this register. Bit7: UNUSED. Read = 0. Write = don’t care. Bit6: FERROR: Flash Error ...

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C8051F330/1/2/3/4/5 Table 10.1. Reset Electrical Characteristics –40 to +85 °C unless otherwise specified. Parameter I OL RST Output Low Voltage V DD RST Input High Voltage RST Input Low Voltage RST Input Pullup Current RST = 0 POR ...

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Flash Memory On-chip, re-programmable Flash memory is included for program code and non-volatile data storage. The Flash memory can be programmed in-system, a single byte at a time, through the C2 interface or by soft- ware using the MOVX ...

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C8051F330/1/2/3/4/5 11.1.3. Flash Write Procedure Flash bytes are programmed by software with the following sequence: Step 1. Disable interrupts (recommended). Step 2. Erase the 512-byte Flash page containing the target location, as described in 11.1.2 . Step 3. Set the ...

Page 102

Security Options The CIP-51 provides security options to protect the Flash memory from inadvertent modification by soft- ware as well as to prevent the viewing of proprietary program code and constants. The Program Store Write Enable (bit PSWE in ...

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C8051F330/1/2/3/4/5 The level of Flash security depends on the Flash access method. The three Flash access methods that can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on unlocked pages, and user firmware ...

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Flash Write and Erase Guidelines Any system which contains routines which write or erase Flash memory from software involves some risk that the write or erase routines will execute unintentionally if the CPU is operating outside its specified operating ...

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C8051F330/1/2/3/4/5 viced in priority order after the Flash operation has been completed and interrupts have been re-enabled by software. 10. Make certain that the Flash write and erase pointer variables are not located in XRAM. See your compiler documentation for ...

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SFR Definition 11.2. FLKEY: Flash Lock and Key R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: FLKEY: Flash Lock and Key Register Write: This register provides a lock and key function for Flash erasures and writes. Flash writes and erases are ...

Page 107

External RAM The C8051F330/1/2/3/4/5 devices include 512 bytes of RAM mapped into the external data memory space. All of these address locations may be accessed using the external move instruction (MOVX) and the data pointer (DPTR), or using MOVX ...

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C8051F330/1/2/3/4/5 112 Rev. 1.7 ...

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Oscillators C8051F330/1/2/3/4/5 devices include a programmable internal high-frequency oscillator, a programmable internal low-frequency oscillator, and an external oscillator drive circuit. The internal high-frequency oscilla- tor can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as shown in ...

Page 110

C8051F330/1/2/3/4/5 SFR Definition 13.1. OSCICL: Internal H-F Oscillator Calibration R R/W R/W - Bit7 Bit6 Bit5 Bit7: UNUSED. Read = 0. Write = don’t care. Bits 6–0: OSCICL: Internal Oscillator Calibration Register. This register determines the internal oscillator period. When ...

Page 111

Programmable Internal Low-Frequency (L-F) Oscillator All C8051F330/1/2/3/4/5 devices include a programmable low-frequency internal oscillator, which is cali- brated to a nominal frequency of 80 kHz. The low-frequency oscillator circuit includes a divider that can be changed to divide the ...

Page 112

C8051F330/1/2/3/4/5 13.3. External Oscillator Drive Circuit The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor network. A CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crys- tal/resonator ...

Page 113

SFR Definition 13.4. OSCXCN: External Oscillator Control R R/W R/W XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 Bit7 Bit6 Bit5 Bit7: XTLVLD: Crystal Oscillator Valid Flag. (Read only when XOSCMD = 11x.) 0: Crystal Oscillator is unused or not yet stable. 1: Crystal ...

Page 114

C8051F330/1/2/3/4/5 13.3.1. External Crystal Example If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 13.1, Option 1. The External Oscillator Frequency Control value (XFCN) ...

Page 115

The capacitors shown in the external crystal configuration provide the load capacitance required by the crystal for correct oscillation. These capacitors are "in series" as seen by the crystal and "in parallel" with the stray capacitance of the XTAL1 and ...

Page 116

C8051F330/1/2/3/4/5 13.3.2. External RC Example network is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 13.1, Option 2. The capacitor should be no greater than 100 pF; ...

Page 117

System Clock Selection The internal oscillator requires little start-up time and may be selected as the system clock immediately fol- lowing the OSCICN write that enables the internal oscillator. External crystals and ceramic resonators typ- ically require a start-up ...

Page 118

C8051F330/1/2/3/4/5 Table 13.1. Internal Oscillator Electrical Characteristics V = 2 –40 to +85 °C unless otherwise specified DD A Parameter Internal High-Frequency Oscillator (Using Factory-Calibrated Settings) Oscillator Frequency IFCN = 11b Oscillator Supply Current  ...

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Port Input/Output Digital and analog resources are available through 17 I/O pins. Port pins are organized as two byte-wide Ports and one 1-bit Port. Each of the Port pins can be defined as general-purpose I/O (GPIO) or analog input; ...

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C8051F330/1/2/3/4/5 /WEAK-PULLUP PUSH-PULL /PORT-OUTENABLE PORT-OUTPUT Analog Select ANALOG INPUT PORT-INPUT Figure 14.2. Port I/O Cell Block Diagram 124 VDD VDD (WEAK) GND Rev. 1.7 PORT PAD ...

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Priority Crossbar Decoder The Priority Crossbar Decoder (Figure 14.3) assigns a priority to each I/O function, starting at the top with UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that resource (excluding ...

Page 122

C8051F330/1/2/3/4/5 SF Signals VREF IDA x1 x2 PIN I TX0 RX0 SCK MISO MOSI NSS* SDA SCL CP0 CP0A SYSCLK CEX0 CEX1 CEX2 ECI P0SKIP[0:7] Port pin potentially available to ...

Page 123

Port I/O Initialization Port I/O initialization consists of the following steps: Step 1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (PnMDIN). Step 2. Select the output mode (open-drain or ...

Page 124

C8051F330/1/2/3/4/5 SFR Definition 14.1. XBR0: Port I/O Crossbar Register R CP0AE Bit7 Bit6 Bit5 Bits7–6: UNUSED. Read = 00b, Write = don’t care. Bit5: CP0AE: Comparator0 Asynchronous Output Enable 0: Asynchronous CP0 unavailable at Port ...

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SFR Definition 14.2. XBR1: Port I/O Crossbar Register 1 R/W R/W R/W WEAKPUD XBARE T1E Bit7 Bit6 Bit5 Bit7: WEAKPUD: Port I/O Weak Pullup Disable. 0: Weak Pullups enabled (except for Ports whose I/O are configured as analog input). 1: ...

Page 126

C8051F330/1/2/3/4/5 SFR Definition 14.3. P0: Port0 R/W R/W R/W P0.7 P0.6 P0.5 Bit7 Bit6 Bit5 Bits7–0: P0.[7:0] Write - Output appears on I/O pins per Crossbar Registers. 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P0MDOUT.n ...

Page 127

SFR Definition 14.5. P0MDOUT: Port0 Output Mode R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: Output Configuration Bits for P0.7–P0.0 (respectively): ignored if corresponding bit in regis- ter P0MDIN is logic 0. 0: Corresponding P0.n Output is open-drain. 1: Corresponding P0.n ...

Page 128

C8051F330/1/2/3/4/5 SFR Definition 14.8. P1MDIN: Port1 Input Mode R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: Analog Input Configuration Bits for P1.7–P1.0 (respectively). Port pins configured as analog inputs have their weak pullup, digital driver, and digital receiver disabled. 0: Corresponding ...

Page 129

SFR Definition 14.11. P2: Port2 Bit7 Bit6 Bit5 Bits7–1: Unused. Read = 0000000b. Write = don’t care. Bit0: P2.0 Write - Output appears on I/O pins per Crossbar Registers. 0: Logic Low Output. 1: ...

Page 130

C8051F330/1/2/3/4/5 Table 14.1. Port I/O DC Electrical Characteristics V = 2.7 to 3.6 V, –40 to +85 °C unless otherwise specified. DD Parameters I = –3 mA, Port I/O push-pull –10 µA, Port I/O push-pull Output High ...

Page 131

SMBus The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specification, version 1.1, and compatible with the I2C serial bus. Reads and writes to the interface by the system ...

Page 132

C8051F330/1/2/3/4/5 15.1. Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents: 1. The I2C-Bus and How to Use It (including specifications), Philips Semiconductor. 2. The I2C-Bus Specification—Version 2.0, Philips Semiconductor. 3. ...

Page 133

The direction bit (R/W) occupies the least-significant bit position of the address byte. The direction bit is set to logic 1 to indicate a "READ" operation and cleared to logic 0 to indicate a "WRITE" operation. All transactions are initiated ...

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C8051F330/1/2/3/4/5 15.3.2. Clock Low Extension SMBus provides a clock synchronization mechanism, similar to I2C, which allows devices with different speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow slower slave ...

Page 135

SMBus configuration options include: • Timeout detection (SCL Low Timeout and/or Bus Free Timeout) • SDA setup and hold time extensions • Slave event enable/disable • Clock source selection These options are selected in the SMB0CF register, as described in ...

Page 136

C8051F330/1/2/3/4/5 15.4.1. SMBus Configuration Register The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes, select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is set, the ...

Page 137

Figure 15.4 shows the typical SCL generation described by Equation 15.2. Notice that T twice as large The actual SCL output may vary due to other devices on the bus (SCL may be LOW extended low by ...

Page 138

C8051F330/1/2/3/4/5 SFR Definition 15.1. SMB0CF: SMBus Clock/Configuration R/W R/W R ENSMB INH BUSY Bit7 Bit6 Bit5 Bit7: ENSMB: SMBus Enable. This bit enables/disables the SMBus interface. When enabled, the interface constantly mon- itors the SDA and SCL pins. 0: SMBus ...

Page 139

SMB0CN Control Register SMB0CN is used to control the interface and to provide status information (see SFR Definition 15.2). The higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to ...

Page 140

C8051F330/1/2/3/4/5 SFR Definition 15.2. SMB0CN: SMBus Control R R R/W MASTER TXMODE STA Bit7 Bit6 Bit5 Bit7: MASTER: SMBus Master/Slave Indicator. This read-only bit indicates when the SMBus is operating as a master. 0: SMBus operating in Slave Mode. 1: ...

Page 141

Table 15.3. Sources for Hardware Changes to SMB0CN Bit Set by Hardware When: MASTER • A START is generated. • START is generated. TXMODE • SMB0DAT is written before the start of an SMBus frame. • A START followed by ...

Page 142

C8051F330/1/2/3/4/5 15.4.3. Data Register The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received. Software may safely read or write to the data register when the SI flag is ...

Page 143

S SLA W A Data Byte Interrupt Interrupt Received by SMBus Interface Transmitted by SMBus Interface Figure 15.5. Typical Master Transmitter Sequence Rev. 1.7 C8051F330/1/2/3/4/5 A Data Byte A P Interrupt Interrupt S = START P = STOP A = ...

Page 144

C8051F330/1/2/3/4/5 15.5.2. Master Receiver Mode Serial data is received on SDA while the serial clock is output on SCL. The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the ...

Page 145

Slave Receiver Mode Serial data is received on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode when a START followed by a slave address and ...

Page 146

C8051F330/1/2/3/4/5 15.5.4. Slave Transmitter Mode Serial data is transmitted on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START ...

Page 147

Table 15.4. SMBus Status Decoding Values Read Current SMbus State 1110 master START was generated. A master data or address byte was transmitted; NACK received. 1100 A master data or address byte 0 ...

Page 148

C8051F330/1/2/3/4/5 Table 15.4. SMBus Status Decoding Values Read Current SMbus State A slave byte was transmitted NACK received. A slave byte was transmitted; 0100 ACK received. A Slave byte was transmitted ...

Page 149

UART0 UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details in Section “16.1. ...

Page 150

C8051F330/1/2/3/4/5 16.1. Enhanced Baud Rate Generation The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer ...

Page 151

Operational Modes UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown below. Figure 16.3. UART Interconnect Diagram 16.2.1. 8-Bit UART 8-Bit UART ...

Page 152

C8051F330/1/2/3/4/5 16.2.2. 9-Bit UART 9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programma- ble ninth data bit, and a stop bit. The state of the ninth transmit ...

Page 153

Master Slave Device Device Figure 16.6. UART Multi-Processor Mode Interconnect Diagram C8051F330/1/2/3/4/5 Slave Slave Device Device Rev. 1.7 V+ 157 ...

Page 154

C8051F330/1/2/3/4/5 SFR Definition 16.1. SCON0: Serial Port 0 Control R/W R R/W S0MODE - MCE0 Bit7 Bit6 Bit5 Bit7: S0MODE: Serial Port 0 Operation Mode. This bit selects the UART0 Operation Mode. 0: 8-bit UART with Variable Baud Rate. 1: ...

Page 155

SFR Definition 16.2. SBUF0: Serial (UART0) Port Data Buffer R/W R/W R/W Bit7 Bit6 Bit5 Bits7 – 0: SBUF0[7:0]: Serial Data Buffer Bits 7 – 0 (MSB – LSB) This SFR accesses two registers; a transmit shift register and a ...

Page 156

C8051F330/1/2/3/4/5 Table 16.1. Timer Settings for Standard Baud Rates Using the Internal 24.5 MHz Target Baud Rate Baud Rate % Error (bps) 230400 –0.32% 115200 –0.32% 57600 0.15% 28800 –0.32% 14400 0.15% 9600 –0.32% 2400 –0.32% 1200 0.15% Notes: – ...

Page 157

Table 16.3. Timer Settings for Standard Baud Rates Using an External 22.1184 MHz Target Baud Rate Baud Rate % Error (bps) 230400 0.00% 115200 0.00% 57600 0.00% 28800 0.00% 14400 0.00% 9600 0.00% 2400 0.00% 1200 0.00% 230400 0.00% 115200 ...

Page 158

C8051F330/1/2/3/4/5 Table 16.5. Timer Settings for Standard Baud Rates Using an External 11.0592 MHz Target Baud Rate Baud Rate % Error (bps) 230400 0.00% 115200 0.00% 57600 0.00% 28800 0.00% 14400 0.00% 9600 0.00% 2400 0.00% 1200 0.00% 230400 0.00% ...

Page 159

Enhanced Serial Peripheral Interface (SPI0) The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports mul- tiple ...

Page 160

C8051F330/1/2/3/4/5 17.1. Signal Descriptions The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below. 17.1.1. Master Out, Slave In (MOSI) The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave ...

Page 161

SPI0 Master Mode Operation A SPI master device initiates all data transfers on a SPI bus. SPI0 is placed in master mode by setting the Master Enable flag (MSTEN, SPI0CN.6). Writing a byte of data to the SPI0 data ...

Page 162

C8051F330/1/2/3/4/5 Master Device 1 Figure 17.2. Multiple-Master Mode Connection Diagram Master Device Figure 17.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Master Device GPIO Figure 17.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection 166 NSS GPIO ...

Page 163

SPI0 Slave Mode Operation When SPI0 is enabled and not configured as a master, it will operate as a SPI slave slave, bytes are shifted in through the MOSI pin and out through the MISO pin by ...

Page 164

C8051F330/1/2/3/4/5 17.5. Serial Clock Timing Four combinations of serial clock phase and polarity can be selected using the clock control bits in the SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases (edge used to ...

Page 165

SCK (CKPOL=0, CKPHA=0) SCK (CKPOL=1, CKPHA=0) MOSI MSB MISO MSB NSS (4-Wire Mode) Figure 17.6. Slave Mode Data/Clock Timing (CKPHA = 0) SCK (CKPOL=0, CKPHA=1) SCK (CKPOL=1, CKPHA=1) MOSI MSB MISO MSB NSS (4-Wire Mode) Figure 17.7. Slave Mode Data/Clock ...

Page 166

C8051F330/1/2/3/4/5 SFR Definition 17.1. SPI0CFG: SPI0 Configuration R R/W R/W SPIBSY MSTEN CKPHA Bit7 Bit6 Bit5 Bit 7: SPIBSY: SPI Busy (read only). This bit is set to logic 1 when a SPI transfer is in progress (Master or slave ...

Page 167

SFR Definition 17.2. SPI0CN: SPI0 Control R/W R/W R/W SPIF WCOL MODF RXOVRN NSSMD1 NSSMD0 Bit7 Bit6 Bit5 Bit 7: SPIF: SPI0 Interrupt Flag. This bit is set to logic 1 by hardware at the end of a data transfer. ...

Page 168

C8051F330/1/2/3/4/5 SFR Definition 17.3. SPI0CKR: SPI0 Clock Rate R/W R/W R/W SCR7 SCR6 SCR5 Bit7 Bit6 Bit5 Bits 7 – 0: SCR7 – SCR0: SPI0 Clock Rate. These bits determine the frequency of the SCK output when the SPI0 module ...

Page 169

SCK* T MCKH MISO MOSI * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 17.8. SPI Master Timing (CKPHA = 0) SCK* T MCKH T MIS MISO MOSI * SCK is ...

Page 170

C8051F330/1/2/3/4/5 NSS T SE SCK* T CKH MOSI T SEZ MISO * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 17.10. SPI Slave Timing (CKPHA = 0) NSS T SE SCK* ...

Page 171

Table 17.1. SPI Slave Timing Parameters Parameter Description * Master Mode Timing (See Figure 17.8 and Figure 17.9) T SCK High Time MCKH T SCK Low Time MCKL T MISO Valid to SCK Shift Edge MIS T SCK Shift Edge ...

Page 172

C8051F330/1/2/3/4/5 176 Rev. 1.7 ...

Page 173

Timers Each MCU includes four counter/timers: two are 16-bit counter/timers compatible with those found in the standard 8051, and two are 16-bit auto-reload timer for use with the ADC, SMBus, or for general purpose use. These timers can be ...

Page 174

C8051F330/1/2/3/4/5 The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to “14.1. Priority Crossbar Decoder” on page 125 ...

Page 175

Mode 2: 8-bit Counter/Timer with Auto-Reload Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start value. TL0 holds the count and TH0 holds the reload value. When the counter ...

Page 176

C8051F330/1/2/3/4/5 18.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The coun- ter/timer in TL0 is controlled using the Timer 0 control/status bits ...

Page 177

SFR Definition 18.1. TCON: Timer Control R/W R/W R/W TF1 TR1 TF0 Bit7 Bit6 Bit5 Bit7: TF1: Timer 1 Overflow Flag. Set by hardware when Timer 1 overflows. This flag can be cleared by software but is auto- matically cleared ...

Page 178

C8051F330/1/2/3/4/5 SFR Definition 18.2. TMOD: Timer Mode R/W R/W R/W GATE1 C/T1 T1M1 Bit7 Bit6 Bit5 Bit7: GATE1: Timer 1 Gate Control. 0: Timer 1 enabled when TR1 = 1 irrespective of /INT1 logic level. 1: Timer 1 enabled only ...

Page 179

SFR Definition 18.3. CKCON: Clock Control R/W R/W R/W T3MH T3ML T2MH Bit7 Bit6 Bit5 Bit7: T3MH: Timer 3 High Byte Clock Select. This bit selects the clock supplied to the Timer 3 high byte if Timer 3 is configured ...

Page 180

C8051F330/1/2/3/4/5 SFR Definition 18.4. TL0: Timer 0 Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7 – 0: TL0: Timer 0 Low Byte. The TL0 register is the low byte of the 16-bit Timer 0. SFR Definition 18.5. TL1: ...

Page 181

Timer 2 Timer 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T2SPLIT bit (TMR2CN.3) defines the ...

Page 182

C8051F330/1/2/3/4/5 18.2.2. 8-bit Timers with Auto-Reload When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers oper- ate in auto-reload mode as shown in Figure 18.5. TMR2RLL holds the reload value for TMR2L; ...

Page 183

SFR Definition 18.8. TMR2CN: Timer 2 Control R/W R/W R/W TF2H TF2L TF2LEN TF2CEN Bit7 Bit6 Bit5 Bit7: TF2H: Timer 2 High Byte Overflow Flag. Set by hardware when the Timer 2 high byte overflows from 0xFF to 0x00. In ...

Page 184

C8051F330/1/2/3/4/5 SFR Definition 18.9. TMR2RLL: Timer 2 Reload Register Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7 – 0: TMR2RLL: Timer 2 Reload Register Low Byte. TMR2RLL holds the low byte of the reload value for Timer 2. ...

Page 185

Timer 3 Timer 16-bit timer formed by two 8-bit SFRs: TMR3L (low byte) and TMR3H (high byte). Timer 3 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T3SPLIT bit (TMR3CN.3) defines the ...

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C8051F330/1/2/3/4/5 18.3.2. 8-bit Timers with Auto-Reload When T3SPLIT is set, Timer 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit timers oper- ate in auto-reload mode as shown in Figure 18.7. TMR3RLL holds the reload value for TMR3L; ...

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SFR Definition 18.13. TMR3CN: Timer 3 Control R/W R/W R/W TF3H TF3L TF3LEN TF3CEN Bit7 Bit6 Bit5 Bit7: TF3H: Timer 3 High Byte Overflow Flag. Set by hardware when the Timer 3 high byte overflows from 0xFF to 0x00. In ...

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C8051F330/1/2/3/4/5 SFR Definition 18.14. TMR3RLL: Timer 3 Reload Register Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7 – 0: TMR3RLL: Timer 3 Reload Register Low Byte. TMR3RLL holds the low byte of the reload value for Timer 3. ...

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Programmable Counter Array The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer and three 16-bit capture/compare modules. Each capture/compare module has ...

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C8051F330/1/2/3/4/5 19.1. PCA Counter/Timer The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte (MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches the value of ...

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Capture/Compare Modules Each module can be configured to operate independently in one of six operation modes: Edge-triggered Capture, Software Timer, High Speed Output, Frequency Output, 8-Bit Pulse Width Modulator, or 16-Bit Pulse Width Modulator. Each module has Special Function ...

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C8051F330/1/2/3/4/5 19.2.1. Edge-triggered Capture Mode In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA coun- ter/timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and PCA0CPHn). ...

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Software Timer (Compare) Mode In Software Timer mode, the PCA counter/timer value is compared to the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1 and ...

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C8051F330/1/2/3/4/5 19.2.3. High-Speed Output Mode In High-Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn) Setting the TOGn, MATn, and ECOMn ...

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Frequency Output Mode Frequency Output Mode produces a programmable-frequency square wave on the module’s associated CEXn pin. The capture/compare module high byte holds the number of PCA clocks to count before the out- put is toggled. The frequency of ...

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C8051F330/1/2/3/4/5 19.2.5. 8-Bit Pulse Width Modulator Mode Each module can be used independently to generate a pulse width modulated (PWM) output on its associ- ated CEXn pin. The frequency of the output is dependent on the timebase for the PCA ...

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Pulse Width Modulator Mode A PCA module may also be operated in 16-Bit PWM mode. In this mode, the 16-bit capture/compare mod- ule defines the number of PCA clocks for the low time of the PWM signal. When ...

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C8051F330/1/2/3/4/5 19.3.1. Watchdog Timer Operation While the WDT is enabled: • PCA counter is forced on. • Writes to PCA0L and PCA0H are not allowed. • PCA clock source bits (CPS2 – CPS0) are frozen. • PCA Idle control bit ...

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Note that the 8-bit offset held in PCA0CPH2 is compared to the upper byte of the 16-bit PCA counter. This offset value is the number of PCA0L overflows before a reset 256 PCA clocks may pass before the ...

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C8051F330/1/2/3/4/5 Table 19.4. Watchdog Timer Timeout Intervals System Clock (Hz) 24,500,000 24,500,000 24,500,000 18,432,000 18,432,000 18,432,000 11,059,200 11,059,200 11,059,200 3,062,500 3,062,500 3,062,500 32,000 32,000 32,000 Notes: 1. Assumes SYSCLK/12 as the PCA clock source, and a PCA0L value of 0x00 ...

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