C8051F330DK Silicon Laboratories Inc, C8051F330DK Datasheet - Page 76

• Manufacturer Part Number: C8051F330DK
• Description: DEV KIT FOR C8051F330/F331
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F330DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F33x
• Interface Type: RS-232
• Operating Supply Voltage: 7 V to 15 V
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F330
• Silicon Family Name: C8051F33x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051F330, C8051F331
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1264

9.2.6. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The
CIP-51 duplicates the SFRs found in a typical 8051 implementation as well as implementing additional
SFRs used to configure and access the sub-systems unique to the MCU. This allows the addition of new
functionality while retaining compatibility with the MCS-51™ instruction set. Table 9.2 lists the SFRs imple-
mented in the CIP-51 System Controller.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, SCON0, IE, etc.) are bit-
addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate
effect and should be avoided. Refer to the corresponding pages of the data sheet, as indicated in
Table 9.3, for a detailed description of each register.
E8 ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2
E0
D8 PCA0CN
D0
C8 TMR2CN
C0 SMB0CN
B8
B0
A8
A0
F8
F0
98
90
88
80
(bit addressable)
SPI0CN
SCON0
TCON
PSW
ACC
0(8)
P2
P1
P0
IP
IE
B
Table 9.2. Special Function Register (SFR) Memory Map
OSCXCN
SPI0CFG
PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2
TMR3CN
REF0CN
SMB0CF
P0MDIN
CLKSEL
IDA0CN
PCA0L
SBUF0
TMOD
XBR0
1(9)
SP
TMR2RLL TMR2RLH
SMB0DAT ADC0GTL ADC0GTH ADC0LTL
TMR3RLL TMR3RLH
SPI0CKR
P1MDIN
OSCICN
EMI0CN
AMX0N
PCA0H
XBR1
DPL
2(A)
TL0
PCA0CPL0 PCA0CPH0
OSCLCN
SPI0DAT
CPT0CN
OSCICL
AMX0P
DPH
3(B)
TL1
Rev. 1.7
P0MDOUT P1MDOUT P2MDOUT
ADC0CF
P0SKIP
IT01CF
TMR2L
TMR3L
TH0
4(C)
C8051F330/1/2/3/4/5
CPT0MD
P1SKIP
TMR2H
TMR3H
ADC0L
TH1
5(D)
ADC0LTH
CKCON
ADC0H
FLSCL
IDA0L
EIP1
EIE1
6(E)
VDM0CN
RSTSRC
CPT0MX
FLKEY
PSCTL
IDA0H
PCON
7(F)
79