C8051F330DK Silicon Laboratories Inc, C8051F330DK Datasheet - Page 95

• Manufacturer Part Number: C8051F330DK
• Description: DEV KIT FOR C8051F330/F331
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F330DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F33x
• Interface Type: RS-232
• Operating Supply Voltage: 7 V to 15 V
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F330
• Silicon Family Name: C8051F33x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051F330, C8051F331
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1264

C8051F330/1/2/3/4/5
10.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin is driven low until V
V
increases (V
power-on and V
cause the device to be released from reset before V
1 ms, the power-on reset delay (T
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000) software can
read the PORSF flag to determine if a power-up was the cause of reset. The content of internal data mem-
ory should be assumed to be undefined after a power-on reset. The V
power-on reset.
10.2. Power-Fail Reset/V
When a power-down transition or power irregularity causes V
monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 10.2). When V
to a level above V
memory contents are not altered by the power-fail reset, it is impossible to determine if V
the level required for data retention. If the PORSF flag reads ‘1’, the data may no longer be valid. The V
monitor is disabled after power-on resets; however its defined state (enabled/disabled) is not altered by
any other reset source. For example, if the V
V
98
RST
DD
monitor will still be enabled after the reset.
. A delay occurs before the device is released from reset; the delay decreases as the V
DD
ramp time is defined as how fast V
DD
Logic HIGH
Logic LOW
RST
Figure 10.2. Power-On and V
monitor reset timing. The maximum V
2.70
2.55
2.0
1.0
, the CIP-51 will be released from the reset state. Note that even though internal data
/RST
DD
V
PORDelay
RST
Monitor
Power-On
Reset
) is typically less than 0.3 ms.
DD
T
PORDelay
monitor is enabled and a software reset is performed, the
Rev. 1.7
DD
DD
DD
reaches the V
ramps from 0 V to V
DD
Monitor Reset Timing
ramp time is 1 ms; slower ramp times may
DD
to drop below V
Monitor
Reset
VDD
RST
DD
level. For ramp times less than
monitor is disabled following a
RST
). Figure 10.2. plots the
RST
VDD
, the power supply
DD
DD
t
dropped below
settles above
DD
ramp time
DD
returns
DD