MAX11132ATI+ Maxim Integrated, MAX11132ATI+ Datasheet - Page 21

• Manufacturer Part Number: MAX11132ATI+
• Description: Analog to Digital Converters - ADC 12Bit 8Ch 3Msps Precision ADC
• Manufacturer: Maxim Integrated

Specifications of MAX11132ATI+

• Rohs: yes
• Number Of Channels: 8/4
• Architecture: SAR
• Conversion Rate: 3 MSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Pseudo-Differential
• Snr: 72.3 dB
• Interface Type: 3-Wire, QSPI, SPI
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: TQFN-28
• Maximum Power Dissipation: 2758 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 1 V

In averaging mode, the device performs the specified
number of conversions and returns the average for each
requested result in the FIFO. The averaging mode works
with internal clock only.
When the Unipolar or Bipolar registers are configured
as pseudo-differential or fully differential, the analog
input pairs are repeated in this automated mode. For
example, if N is set to 15 to scan all 16 channels and
all analog input pairs are configured for fully-differential
conversion, the ADC converts the channels twice. In this
case, the user may avoid dual conversions on input pairs
by implementing Manual mode or using Custom_Int or
Custom_Ext scan modes.
Table 1. Register Access and Control
Table 2. ADC Mode Control Register
Maxim Integrated
ADC Mode Control
ADC Configuration
Unipolar
Bipolar
RANGE
Custom Scan0
Custom Scan1
SampleSet
Reserved. Do not use.
CHSEL[3:0]
REG_CNTL
RESET[1:0]
BIT NAME
SCAN[3:0]
REGISTER NAME
Scan Modes and Unipolar/Bipolar Setting
14:11
10:7
BIT
6:5
15
DEFAULT
STATE
0001
0000
00
0
3Msps, Low-Power, Serial 12-/10-Bit,
BIT 15
Averaging Mode
0
1
1
1
1
1
1
1
1
Set to 0 to select the ADC Mode Control register
ADC Scan Control register (Table 3)
Analog Input Channel Select register (Table 4).
See Table 3 to determine which modes use CHSEL[3:0] for the channel scan
instruction.
RESET1
0
0
1
1
REGISTER IDENTIFICATION CODE
BIT 14
DIN
0
0
0
0
0
0
0
1
RESET0
BIT 13
0
1
0
1
DIN
The MAX11129–MAX11132 communicate between the
internal registers and the external circuitry through the
SPI-/QSPI-compatible serial interface.
register access and control.
detail the various functions and configurations.
For ADC mode control, set bit 15 of the register code
identification to zero. The ADC Mode Control register
determines when and under what scan condition the
ADC operates.
To set the ADC data configuration, set the bit 15 of the
register code identification to one.
0
0
0
0
1
1
1
1
MAX11129–MAX11132
No reset
Reset the FIFO only (resets to zero)
Reset all registers to default settings (includes FIFO)
Unused
BIT 12
8-/16-Channel ADCs
DIN
FUNCTION
0
0
1
1
0
0
1
1
Register Descriptions
BIT 11
DIN
0
1
0
1
0
1
0
1
FUNCTION
Table 2
DIN ≡ DATA INPUTS
Table 1
through
BIT [10:0]
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DIN
details the
Table 14
21