IS46TR16128A-125KBLA1 ISSI, IS46TR16128A-125KBLA1 Datasheet - Page 13

• Manufacturer Part Number: IS46TR16128A-125KBLA1
• Description: DRAM 2G, 1.5V, 1600MT/s 128Mx16 DDR3
• Manufacturer: ISSI

Specifications of IS46TR16128A-125KBLA1

• Rohs: yes
• Data Bus Width: 16 bit
• Organization: 128 M x 16
• Package / Case: FBGA-96
• Memory Size: 2 Gbit
• Maximum Clock Frequency: 933 MHz
• Access Time: 13.125 ns
• Supply Voltage - Max: 1.575 V
• Supply Voltage - Min: 1.425 V
• Maximum Operating Current: 70 mA
• Maximum Operating Temperature: + 95 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

IS43/46TR16128A, IS43/46TR16128AL,
IS43/46TR82560A, IS43/46TR82560AL
(in ns) and rounding up to the next integer: WRmin[cycles] = Roundup(tWR[ns]/tCK[ns]). The WR must be programmed to
be equal to or larger than tWR(min).
2.3.2.6 Precharge PD DLL
MR0 (bit A12) is used to select the DLL usage during precharge power-down mode. When MR0 (A12 = 0), or ‘slow-exit’,
the DLL is frozen after entering precharge power-down (for potential power savings) and upon exit requires tXPDLL to be
met prior to the next valid command. When MR0 (A12 = 1), or ‘fast-exit’, the DLL is maintained after entering precharge
power-down and upon exiting power-down requires tXP to be met prior to the next valid command.
2.3.3 Mode Register MR1
The Mode Register MR1 stores the data for enabling or disabling the DLL, output driver strength, Rtt_Nom impedance,
additive latency, Write leveling enable, TDQS enable and Qoff. The Mode Register 1 is written by asserting low on CS#,
RAS#, CAS#, WE#, high on BA0 and low on BA1 and BA2, while controlling the states of address pins according to
Figure 2.3.3.
* 1 : A8, A10, A13, and A14 must be programmed to 0 during MRS.
* TDQS must be disabled for x16 option.
2.3.3.1 DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning
to normal operation after having the DLL disabled. During normal operation (DLL-on) with MR1 (A0 = 0), the DLL is
automatically disabled when entering Self-Refresh operation and is automatically re-enabled upon exit of Self-Refresh
operation. Any time the DLL is enabled and subsequently reset, tDLLK clock cycles must occur before a Read or
synchronous ODT command can be issued to allow time for the internal clock to be synchronized with the external clock.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00A
11/14/2012
*2: Outputs disabled - DQs, DQSs, DQS#s.
BA1 BA0
BA2 BA1 BA0
A11
A12
0
1
0
1
0
0
1
1
0
0
0
1
0
1
TDQS enable
Disabled
Enabled
Output buffer disabled
1
Output buffer enabled
MR Select
MR0
MR1
MR2
MR3
Qoff
A14-A13
0*
A4
*2
0
0
1
1
1
A7
A3
0
1
0
1
0
1
*2
Qoff TDQS 0*
A12
Write leveling enable
Additive Latency
0 (AL disabled)
A11
Reserved
Disabled
Enabled
CL-1
CL-2
A10
1
Figure 2.3.3 MR1 Definition
A9
Rtt
0*
A8
1
Note: RZQ = 240 
*3:In Write leveling Mode (MR1[bit7] = 1) with
MR1[bit12]=1, all RTT_Nom settings are allowed; in
Write Leveling Mode (MR1[bit7] = 1) with
MR1[bit12]=0, only RTT_Nom settings of RZQ/2,
RZQ/4 and RZQ/6 are allowed.
*4:If RTT_Nom is used during Writes, only the
values RZQ/2, RZQ/4 and RZQ/6 are allowed.
Level Rtt
A7
A9
0
0
0
0
1
1
1
1
A6
A6
0
0
1
1
0
0
1
1
D.I.C
A5
A2
0
1
0
1
0
1
0
1
A4
A5
0
0
1
1
AL
ODT disabled
Rtt_Nom
A3
RZQ/12
A1
Reserved
Reserved
RZQ/8
0
1
0
1
RZQ/4
RZQ/2
RZQ/6
A2
Rtt
*4
*4
*3
Output Driver Impedance Control
D.I.C DLL Mode Register 1
A1
A0 Address Field
Reserved
Reserved
RZQ/6
RZQ/7
A0
0
1
DLL Enable
Disable
Enable
13