MC56F8035VLD Freescale Semiconductor, MC56F8035VLD Datasheet - Page 141

• Manufacturer Part Number: MC56F8035VLD
• Description: Digital Signal Processors & Controllers - DSP, DSC 16 BIT DSPHC 64KB
• Manufacturer: Freescale Semiconductor

Specifications of MC56F8035VLD

• Rohs: yes
• Core: 56800E
• Data Bus Width: 16 bit
• Program Memory Size: 64 KB
• Data Ram Size: 8 KB
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 3
• Device Million Instructions Per Second: 32 MIPs
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Package / Case: LQFP-44
• Mounting Style: SMD/SMT

10.12 Inter-Integrated Circuit Interface (I
Freescale Semiconductor
1. The master mode I
2. The maximum t
3. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
4. A Fast mode I
5. C
SCL Clock Frequency
Hold time (repeated)
START condition. After
this period, the first clock
pulse is generated.
LOW period of the SCL
clock
HIGH period of the SCL
clock
Set-up time for a repeated
START condition
Data hold time for I
devices
Data set-up time
Rise time of both SDA and
SCL signals
Fall time of both SDA and
SCL signals
Set-up time for STOP
condition
Bus free time between
STOP and START
condition
Pulse width of spikes that
must be suppressed by
the input filter
acknowledge this address byte, a negative hold time can result, depending on the edge rates of the SDA and SCL lines.
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal.
If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
t
released.
rmax
b
= total capacitance of the one bus line in pF
Characteristic
+ t
SU; DAT
2
C bus device can be used in a Standard mode I
HD; DAT
= 1000 + 250 = 1250ns (according to the Standard mode I
2
2
C bus
C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
must be met only if the device does not stretch the LOW period (t
Symbol
t
t
t
t
t
HD; STA
HD; DAT
SU; DAT
SU; STO
SU; STA
t
t
f
t
HIGH
LOW
BUF
t
SCL
SP
t
t
r
f
56F8035/56F8025 Data Sheet, Rev. 6
Table 10-17 I
Minimum
250
N/A
4.0
4.7
4.0
4.7
4.0
4.7
0
—
—
Standard Mode
0
1
3
Maximum
2
2
C Timing
3.45
C bus system, but the requirement t
1000
100
300
N/A
—
—
—
—
—
—
—
2
2
2
C bus specification) before the SCL line is
20 +0.1C
20 +0.1C
C) Timing
Minimum
100
1.23
0.6
0.6
0.6
0.6
1.3
0
0
0
1
3, 4
Inter-Integrated Circuit Interface (I2C) Timing
Fast Mode
b
b
5
5
LOW
) of the SCL signal.
Maximum
0.9
400
300
300
50
—
—
—
—
—
—
—
2
SU; DAT
> = 250ns
Unit
kHz
ns
ns
ns
ns
s
s
s
s
s
s
s
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