MC56F8035VLD Freescale Semiconductor, MC56F8035VLD Datasheet - Page 83
MC56F8035VLD
Manufacturer Part Number
MC56F8035VLD
Description
Digital Signal Processors & Controllers - DSP, DSC 16 BIT DSPHC 64KB
Manufacturer
Freescale Semiconductor
Datasheet
1.MC56F8035VLDR.pdf
(161 pages)
Specifications of MC56F8035VLD
Rohs
yes
Core
56800E
Data Bus Width
16 bit
Program Memory Size
64 KB
Data Ram Size
8 KB
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
35
Number Of Timers
3
Device Million Instructions Per Second
32 MIPs
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Package / Case
LQFP-44
Mounting Style
SMD/SMT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC56F8035VLD
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MC56F8035VLDR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
6.3.1
6.3.1.1
This bit field is reserved. Each bit must be set to 0.
6.3.1.2
Note:
6.3.1.3
6.3.1.4
6.3.1.5
Freescale Semiconductor
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0 = OnCE clock to 56800E core enabled when core TAP is enabled
1 = OnCE clock to 56800E core is always enabled
Writing 1 to this field will cause the device to reset
Read is zero
00 = Stop mode will be entered when the 56800E core executes a STOP instruction
01 = The 56800E STOP instruction will not cause entry into Stop mode
10 = Stop mode will be entered when the 56800E core executes a STOP instruction and the
11 = The 56800E STOP instruction will not cause entry into Stop mode and the STOP_DISABLE field is
00 = Wait mode will be entered when the 56800E core executes a WAIT instruction
01 = The 56800E WAIT instruction will not cause entry into Wait mode
10 = Wait mode will be entered when the 56800E core executes a WAIT instruction and the
11 = The 56800E WAIT instruction will not cause entry into Wait mode and the WAIT_DISABLE field is
RESET
Write
Read
Reserved
SIM Control Register (SIM_CTRL)
Using default state “0” is recommended.
write-protected until the next reset
write-protected until the next reset
STOP_DISABLE field is write-protected until the next reset
WAIT_DISABLE field is write-protected until the next reset
Reserved—Bits 15–6
OnCE Enable (ONCEEBL)—Bit 5
Software Reset (SWRST)—Bit 4
Stop Disable (STOP_DISABLE)—Bits 3–2
Wait Disable (WAIT_DISABLE)—Bits 1–0
15
0
0
0
14
0
0
= Read as 0
Figure 6-2 SIM Control Register (SIM_CTRL)
13
Figure 6-1 SIM Register Map Summary
0
0
12
0
0
56F8035/56F8025 Data Sheet, Rev. 6
11
0
0
1
10
0
0
=
Read as 1
9
0
0
8
0
0
7
0
0
6
0
0
= Reserved
ONCE
EBL
5
0
RST
SW
4
0
3
DISABLE
0
STOP_
2
0
Register Descriptions
1
DISABLE
0
WAIT_
0
0
83