MC56F8035VLD Freescale Semiconductor, MC56F8035VLD Datasheet - Page 58
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MC56F8035VLD
Manufacturer Part Number
MC56F8035VLD
Description
Digital Signal Processors & Controllers - DSP, DSC 16 BIT DSPHC 64KB
Manufacturer
Freescale Semiconductor
Datasheet
1.MC56F8035VLDR.pdf
(161 pages)
Specifications of MC56F8035VLD
Rohs
yes
Core
56800E
Data Bus Width
16 bit
Program Memory Size
64 KB
Data Ram Size
8 KB
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
35
Number Of Timers
3
Device Million Instructions Per Second
32 MIPs
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Package / Case
LQFP-44
Mounting Style
SMD/SMT
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC56F8035VLD
Manufacturer:
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Quantity:
10 000
Company:
Part Number:
MC56F8035VLDR
Manufacturer:
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The IPIC bits of the ICTRL register reflect the state of the priority level being presented to the 56800E
core.
5.3.3
Fast interrupts are described in the DSP56800E Reference Manual. The interrupt controller recognizes
Fast Interrupts before the core does.
A Fast Interrupt is defined (to the ITCN) by:
When an interrupt occurs, its vector number is compared with the FIM0 and FIM1 register values. If a
match occurs, and it is a level 2 interrupt, the ITCN handles it as a Fast Interrupt. The ITCN takes the vector
address from the appropriate FIVALn and FIVAHn registers, instead of generating an address that is an
offset from the VBA.
The core then fetches the instruction from the indicated vector address and if it is not a JSR, the core starts
its Fast Interrupt handling.
58
1. Setting the priority of the interrupt as level 2, with the appropriate field in the IPR registers
2. Setting the FIMn register to the appropriate vector number
3. Setting the FIVALn and FIVAHn registers with the address of the code for the
Fast Interrupt Handling
SR[9] (I1) SR[8] (I0)
IPIC_VALUE[1:0]
0
0
1
1
00
01
10
11
Table 5-1 Interrupt Mask Bit Definition
Table 5-2 Interrupt Priority Encoding
0
1
0
1
56F8035/56F8025 Data Sheet, Rev. 6
No interrupt or SWILP
Current Interrupt
Exceptions Permitted
Priority Level
Priority 2 or 3
Priorities 0, 1, 2, 3
Priorities 1, 2, 3
Priority 0
Priority 1
Priorities 2, 3
Priority 3
Exception Priority
Priorities 0, 1, 2, 3
Required Nested
Priorities 1, 2, 3
Exceptions Masked
Priorities 2, 3
Priorities 0, 1, 2
Priority 3
Priorities 0, 1
Priority 0
None
Fast Interrupt
Freescale Semiconductor