dsPIC33FJ32MC104-I/PT Microchip Technology, dsPIC33FJ32MC104-I/PT Datasheet - Page 85
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dsPIC33FJ32MC104-I/PT
Manufacturer Part Number
dsPIC33FJ32MC104-I/PT
Description
Digital Signal Processors & Controllers - DSP, DSC 16bit Mtr Cnt Fam 16 MIPS 32KBFLSH 2KBRAM
Manufacturer
Microchip Technology
Type
dsPIC33FJ32(GP/MC)101/102/104r
Datasheet
1.DSPIC33FJ32GP102-ISO.pdf
(386 pages)
Specifications of dsPIC33FJ32MC104-I/PT
Rohs
yes
Core
dsPIC33F
Data Bus Width
16 bit
Program Memory Size
32 KB
Data Ram Size
2 KB
Maximum Clock Frequency
7.37 MHz, 32 kHz
Number Of Programmable I/os
35
Number Of Timers
5 x 16-bit, 2 x 32-bit
Device Million Instructions Per Second
16 MIPs
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Package / Case
TQFP-44
Mounting Style
SMD/SMT
Family / Core
dsPIC33FJ32(GP/MC)101/102/104
Interface Type
I2C, SPI, UART
Minimum Operating Temperature
- 40 C
On-chip Adc
Yes
Product
DSPs
Program Memory Type
Flash
Supply Current
10 mA
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ32MC104-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- Current page: 85 of 386
- Download datasheet (5Mb)
REGISTER 5-1:
2011-2012 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-7
bit 6
bit 5-4
bit 3-0
Note 1:
R/SO-0
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
WR
U-0
—
2:
(1)
These bits can only be reset on a POR.
All other combinations of NVMOP<3:0> are unimplemented.
WR: Write Control bit
1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is
0 = Program or erase operation is complete and inactive
WREN: Write Enable bit
1 = Enables Flash program/erase operations
0 = Inhibits Flash program/erase operations
WRERR: Write Sequence Error Flag bit
1 = An improper program or erase sequence attempt or termination has occurred (bit is set automatically
0 = The program or erase operation completed normally
Unimplemented: Read as ‘0’
ERASE: Erase/Program Enable bit
1 = Performs the erase operation specified by NVMOP<3:0> on the next WR command
0 = Performs the program operation specified by NVMOP<3:0> on the next WR command
Unimplemented: Read as ‘0’
NVMOP<3:0>: NVM Operation Select bits
If ERASE = 1:
1111 = No operation
1101 = Erase General Segment
1100 = No operation
0011 = No operation
0010 = Memory page erase operation
0001 = No operation
0000 = No operation
If ERASE = 0:
1111 = No operation
1101 = No operation
1100 = No operation
0011 = Memory word program operation
0010 = No operation
0001 = No operation
0000 = No operation
R/W-0
R/W-0
ERASE
WREN
cleared by hardware once operation is complete
on any set attempt of the WR bit)
NVMCON: FLASH MEMORY CONTROL REGISTER
(1)
(1)
SO = Settable Only bit
W = Writable bit
‘1’ = Bit is set
R/W-0
WRERR
U-0
—
(1)
(1)
(1)
U-0
U-0
—
—
(1)
(1)
(1,2)
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
R/W-0
U-0
—
(1)
R/W-0
U-0
—
NVMOP<3:0>
(1)
x = Bit is unknown
R/W-0
U-0
(2)
—
(1)
DS70652E-page 85
R/W-0
U-0
—
(1)
bit 8
bit 0
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