MAX1303BEUP+T Maxim Integrated, MAX1303BEUP+T Datasheet - Page 12

• Manufacturer Part Number: MAX1303BEUP+T
• Description: Analog to Digital Converters - ADC 16-Bit 4Ch 115ksps 4.136V Precision ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1303BEUP+T

• Rohs: yes
• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 115 KSPs
• Resolution: 16 bit
• Input Type: Single-Ended/Differential
• Snr: 90 dB
• Interface Type: MICROWIRE, QSPI, SPI, Serial
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-20
• Maximum Power Dissipation: 879 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Factory Pack Quantity: 2500
• Voltage Reference: Internal, External

4-Channel, ±V
Serial 16-Bit ADC
12
PIN
10
11
12
13
14
15
16
17
18
19
20
______________________________________________________________________________________
1
2
3
4
5
6
7
8
9
REFCAP
DGNDO
DVDDO
AGND1
AGND3
AGND2
AVDD1
AVDD2
SSTRB
NAME
DGND
DOUT
DVDD
SCLK
CH0
CH1
CH2
CH3
REF
DIN
CS
Analog Supply Voltage 1. Connect AVDD1 to a +4.75V to +5.25V power-supply voltage. Bypass AVDD1 to
AGND1 with a 0.1µF capacitor.
Analog Input Channel 0
Analog Input Channel 1
Analog Input Channel 2
Analog Input Channel 3
Active-Low Chip-Select Input. When CS is low, data is clocked into the device from DIN on the rising edge
of SCLK. With CS low, data is clocked out of DOUT on the falling edge of SCLK. When CS is high, activity
on SCLK and DIN is ignored and DOUT is high impedance.
Serial Data Input. When CS is low, data is clocked in on the rising edge of SCLK. When CS is high,
transitions on DIN are ignored.
Serial-Strobe Output. When using the internal clock, SSTRB rising edge transitions indicate that data is
ready to be read from the device. When operating in external clock mode, SSTRB is always low. SSTRB
does not tri-state, regardless of the state of CS, and therefore requires
a dedicated I/O line.
Serial Clock Input. When CS is low, transitions on SCLK clock data into DIN and out of DOUT. When CS is
high, transitions on SCLK are ignored.
Serial Data Output. When CS is low, data is clocked out of DOUT with each falling SCLK transition. When
CS is high, DOUT is high impedance.
Digital I/O Ground. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.
Digital Ground. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.
Digital I/O Supply Voltage Input. Connect DVDDO to a +2.7V to +5.25V power-supply voltage. Bypass
DVDDO to DGNDO with a 0.1µF capacitor.
Digital-Supply Voltage Input. Connect DVDD to a +4.75V to +5.25V power-supply voltage. Bypass DVDD
to DGND with a 0.1µF capacitor.
Bandgap-Voltage Bypass Node. For external reference operation, connect REFCAP to AVDD. For internal
reference operation, bypass REFCAP with a 0.01µF capacitor to AGND1 (V
Reference-Buffer Output/ADC Reference Input. For external reference operation, apply an external
reference voltage from 3.800V to 4.136V to REF. For internal reference operation, bypassing REF with a
1µF capacitor to AGND1 sets V
Analog Signal Ground 3. AGND3 is the ADC negative reference potential. Connect AGND3 to AGND1.
DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.
Analog Supply Voltage 2. Connect AVDD2 to a +4.75V to +5.25V power-supply voltage. Bypass AVDD2 to
AGND2 with a 0.1µF capacitor.
Analog Ground 2. This ground carries approximately five times more current than AGND1. DGND,
DGNDO, AGND3, AGND2, and AGND1 must be connected together.
Analog Ground 1. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.
REF
Multirange Inputs,
REF
= 4.096V ±1%.
FUNCTION
REFCAP
Pin Description
≈ 4.096V).