MAX1303BEUP+T Maxim Integrated, MAX1303BEUP+T Datasheet - Page 14

• Manufacturer Part Number: MAX1303BEUP+T
• Description: Analog to Digital Converters - ADC 16-Bit 4Ch 115ksps 4.136V Precision ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1303BEUP+T

• Rohs: yes
• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 115 KSPs
• Resolution: 16 bit
• Input Type: Single-Ended/Differential
• Snr: 90 dB
• Interface Type: MICROWIRE, QSPI, SPI, Serial
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-20
• Maximum Power Dissipation: 879 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Factory Pack Quantity: 2500
• Voltage Reference: Internal, External

The MAX1303 features a switched-capacitor T/H archi-
tecture that allows the analog input signal to be stored as
charge on sampling capacitors. See Figures 1, 2, and 3
for T/H timing and the sampling instants for each operat-
ing mode. The MAX1303 analog input circuitry buffers
the input signal from the sampling capacitors, resulting
in a constant analog input impedance with varying input
voltage (Figure 4).
Select differential or single-ended conversions using the
associated analog input configuration byte (Table 2).
The analog input signal source must be capable of dri-
ving the ADC’s 6kΩ input resistance (Figure 5).
Figure 5 shows the simplified analog input circuit. The
analog inputs are ±6V fault tolerant and are protected
by back-to-back diodes. The summing junction voltage,
4-Channel, ±V
Serial 16-Bit ADC
Figure 1. External Clock-Mode Conversion (Mode 0)
14
SSTRB
TRACK AND HOLD*
DOUT
SCLK
DIN
CS
ANALOG INPUT
______________________________________________________________________________________
IMPEDANCE
HIGH
*TRACK AND HOLD TIMING IS CONTROLLED BY SCLK.
S
HOLD
C2
C1
C0
Track-and-Hold Circuitry
0
BYTE 1
Analog Input Circuitry
0
0
REF
0
TRACK
t
ACQ
Multirange Inputs,
BYTE 2
f
SAMPLE
≈ f
SAMPLING INSTANT
SCLK
/32
V
voltage:
As a result, the analog input impedance is relatively
constant over the input voltage as shown in Figure 4.
Single-ended conversions are internally referenced to
AGND1 (Tables 3 and 4). In differential mode, IN+ and
IN- are selected according to Tables 3 and 5. When con-
figuring differential channels, the differential pair follows
the analog configuration byte for the positive channel.
For example, to configure CH2 and CH3 for a ±V
ferential conversion, set the CH2 analog configuration
byte for a differential conversion with the ±V
(1010 1100). To initiate a conversion for the CH2 and
CH3 differential pair, issue the command 1010 0000.
B15
V
SJ
SJ
B14
, is a function of the channel’s input common-mode
=
B13
⎛
⎜
⎝
B12
R
1
BYTE 3
B11
R
+
1
R
B10
2
⎞
⎟ ×
⎠
B9
HOLD
B8
2 375
.
B7
B6
V
+
B5
⎛
⎜
⎝
1
B4
+
BYTE 4
B3
⎛
⎜
⎝
R
B2
1
R
+
1
B1
R
2
B0
⎞
⎟
⎠
REF
⎞
⎟ ×
⎠
IMPEDANCE
HIGH
REF
range
V
CM
dif-