MAX1303BEUP+T Maxim Integrated, MAX1303BEUP+T Datasheet - Page 23

• Manufacturer Part Number: MAX1303BEUP+T
• Description: Analog to Digital Converters - ADC 16-Bit 4Ch 115ksps 4.136V Precision ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1303BEUP+T

• Rohs: yes
• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 115 KSPs
• Resolution: 16 bit
• Input Type: Single-Ended/Differential
• Snr: 90 dB
• Interface Type: MICROWIRE, QSPI, SPI, Serial
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-20
• Maximum Power Dissipation: 879 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Factory Pack Quantity: 2500
• Voltage Reference: Internal, External

The slowest maximum throughput rate is achieved with
the external acquisition method. SCLK controls the
acquisition of the analog signal in external acquisition
mode, facilitating precise control over when the analog
signal is captured. The internal clock controls the con-
version of the analog input voltage. The analog input
sampling instant is at the falling edge of the 16th SCLK
(Figure 2).
For the external acquisition mode, CS must remain low
for the first 15 clock cycles and then rise on or after the
falling edge of the 16th SCLK cycle as shown in Figure
2. For optimal performance, idle DIN and SCLK during
the conversion. With careful board layout, transitions at
DIN and SCLK during the conversion have a minimal
impact on the conversion result.
After the conversion is complete, SSTRB asserts high
and CS can be brought low to read the conversion
result. SSTRB returns low on the rising SCLK edge of
the subsequent start bit.
Figure 14. Analog Input Configuration Byte and Mode-Control Byte Timing
Figure 15. DOUT and SSTRB Timing
DOUT
SCLK
NOTE: SSTRB AND CS REMAIN LOW IN EXTERNAL CLOCK MODE (MODE 0).
DIN
CS
IMPEDANCE
t
t
DV
CSS
HIGH
t
DS
SSTRB
DOUT
SCLK
CS
START
t
SSCS
1
External Acquisition Mode (Mode 1)
HIGH IMPEDANCE
______________________________________________________________________________________
t
CL
SEL2
t
CSS
ANALOG INPUT CONFIGURATION BYTE
SEL1
4-Channel, ±V
t
DO
SEL0
MSB
t
CP
DIF/SGL
t
CH
R2
R1
t
CSH
R0
t
t
8
DH
TR
IMPEDANCE
HIGH
In internal clock mode, the internal clock controls both
acquisition and conversion of the analog signal. The inter-
nal clock starts approximately 100ns to 400ns after the
falling edge of the eighth SCLK and has a rate of about
4.5MHz. The analog input sampling instant occurs at the
falling edge of the 11th internal clock signal (Figure 3).
For the internal clock mode, CS must remain low for the
first seven SCLK cycles and then rise on or after the
falling edge of the eighth SCLK cycle. After the conver-
sion is complete, SSTRB asserts high and CS can be
brought low to read the conversion result. SSTRB returns
low on the rising SCLK edge of the subsequent start bit.
As shown in Table 8, set M[2:0] = 100 to reset the
MAX1303 to its default conditions. The default condi-
tions are full power operation with each channel config-
ured for ±V
using external clock mode (mode 0).
As shown in Table 8, when M[2:0] = 110, the device enters
partial power-down mode. In partial power-down, all ana-
log portions of the device are powered down except for the
reference voltage generator and bias supplies.
To exit partial power-down, change the mode by issu-
ing one of the following mode-control bytes (see the
Mode Control section):
• External-clock-mode control byte
• External-acquisition-mode control byte
• Internal-clock-mode control byte
• Reset byte
• Full power-down-mode control byte
This prevents the MAX1303 from inadvertently exiting
partial power-down mode because of a CS glitch in a
noisy digital environment.
REF
t
CSPW
START
1
M2
Multirange Inputs,
REF
Serial 16-Bit ADC
M1
MODE CONTROL BYTE
, bipolar, single-ended conversions
Partial Power-Down Mode (Mode 6)
M0
Internal Clock Mode (Mode 2)
1
0
0
Reset (Mode 4)
0
8
IMPEDANCE
HIGH
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