MAX1246BEEE-T Maxim Integrated, MAX1246BEEE-T Datasheet - Page 6

• Manufacturer Part Number: MAX1246BEEE-T
• Description: Analog to Digital Converters - ADC 12-Bit 4Ch 133ksps 3.6V Precision ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1246BEEE-T

• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 133 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Differential
• Snr: 70 dB
• Interface Type: 4-Wire (SPI, Microwire, QSPI, TMS320)
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QSOP-16
• Maximum Power Dissipation: 667 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 2.5 V

Note 1: Tested at V
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
Note 3: MAX1246—internal reference, offset nulled; MAX1247—external reference (V
Note 4: Ground “on” channel; sine wave applied to all “off” channels.
Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: The common-mode range for the analog inputs is from AGND to V
Note 7: Guaranteed by design. Not subject to production testing.
Note 8: External load should not change during conversion for specified accuracy.
Note 9: ADC performance is limited by the converter’s noise floor, typically 300µVp-p.
Note 10: Measured as
TIMING CHARACTERISTICS
(V
+2.7V, Low-Power, 4-Channel,
Serial 12-Bit ADCs in QSOP-16
(V
6
__________________________________________Typical Operating Characteristics
Acquisition Time
DIN to SCLK Setup
DIN to SCLK Hold
SCLK Fall to Output Data Valid
CS Fall to Output Enable
CS Rise to Output Disable
CS to SCLK Rise Setup
CS to SCLK Rise Hold
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK Fall to SSTRB
CS Fall to SSTRB Output Enable
CS Rise to SSTRB Output Disable
SSTRB Rise to SCLK Rise
DD
DD
_______________________________________________________________________________________
-0.1
-0.2
-0.3
-0.4
-0.5
0.5
0.4
0.3
0.2
0.1
= +2.7V to +3.6V (MAX1246); V
= 3V, VREF = 2.5V, f
0
0
been calibrated.
PARAMETER
INTEGRAL NONLINEARITY
1024
DD
vs. CODE
|
CODE
V
2048
= 2.7V; COM = 0V; unipolar single-ended input mode.
FS
SCLK
(2.7V) - V
3072
= 2MHz, C
FS
DD
SYMBOL
t
(V
SSTRB
t
t
t
t
t
t
ACQ
t
4096
t
t
t
CSH
t
SCK
= +2.7V to +5.25V (MAX1247); T
t
CSS
t
SDV
STR
DH
DO
CH
DS
DV
CL
TR
DD.MAX
LOAD
)
Figure 1
Figure 1
Figure 2
Figure 1
External clock mode only, Figure 1
External clock mode only, Figure 2
Internal clock mode only (Note 7)
= 20pF, T
|
.
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
2.25
2.75
A
INTEGRAL NONLINEARITY
= +25°C, unless otherwise noted.)
vs. SUPPLY VOLTAGE
MAX124_ _C/E
MAX124_ _M
3.25
CONDITIONS
MAX1246
MAX1247
V
3.75
DD
(V)
A
4.25
= T
DD
MIN
.
4.75
to T
5.25
MAX
REF
; unless otherwise noted.)
= +2.500V), offset nulled.
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
-60
MIN
100
100
200
200
1.5
20
20
V
0
0
DD
= 2.7V
MAX1246
INTEGRAL NONLINEARITY
-20
vs. TEMPERATURE
TYP
TEMPERATURE (°C)
20
MAX1247
60
MAX
200
240
240
240
240
240
240
0
100
UNITS
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
140