MAX1246BEEE-T Maxim Integrated, MAX1246BEEE-T Datasheet - Page 9

• Manufacturer Part Number: MAX1246BEEE-T
• Description: Analog to Digital Converters - ADC 12-Bit 4Ch 133ksps 3.6V Precision ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1246BEEE-T

• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 133 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Differential
• Snr: 70 dB
• Interface Type: 4-Wire (SPI, Microwire, QSPI, TMS320)
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QSOP-16
• Maximum Power Dissipation: 667 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 2.5 V

Figure 1. Load Circuits for Enable Time
______________________________________________________________Pin Description
DOUT
PIN
2–5
a) High-Z to V
10
11
12
13
14
15
16
1
6
7
8
9
6kΩ
OH
CH0–CH3
DGND
REFADJ
and V
SSTRB
NAME
DGND
AGND
SHDN
DOUT
SCLK
VREF
COM
V
DIN
CS
DD
OL
_______________________________________________________________________________________
to V
OH
C
50pF
LOAD
Positive Supply Voltage
Sampling Analog Inputs
Ground reference for analog inputs. COM sets zero-code voltage in single-ended mode. Must be
stable to ±0.5LSB.
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1246/MAX1247 down; otherwise, they
are fully operational. Pulling SHDN high puts the reference-buffer amplifier in internal compensation
mode. Letting SHDN float puts the reference-buffer amplifier in external compensation mode.
Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion.
In internal reference mode (MAX1246 only), the reference buffer provides a 2.500V nominal output,
externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling
REFADJ to V
Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to V
Analog Ground
Digital Ground
Serial Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high.
Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX1246/MAX1247 begin the
A/D conversion, and goes high when the conversion is finished. In external clock mode, SSTRB pulses
high for one clock period before the MSB decision. High impedance when CS is high (external clock
mode).
Serial Data Input. Data is clocked in at SCLK’s rising edge.
Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT is
high impedance.
Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets
the conversion speed. (Duty cycle must be 40% to 60%.)
b) High-Z to V
DOUT
DD
V
DD
OL
.
6kΩ
and V
C
DGND
50pF
LOAD
Serial 12-Bit ADCs in QSOP-16
+2.7V, Low-Power, 4-Channel,
OH
to V
OL
Figure 2. Load Circuits for Disable Time
FUNCTION
DOUT
6kΩ
a) V
OH
DGND
to High-Z
C
50pF
LOAD
DOUT
b) V
OL
V
to High-Z
DD
6kΩ
C
50pF
DGND
LOAD
DD
.
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