MAX1077ETC-T Maxim Integrated, MAX1077ETC-T Datasheet - Page 10

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MAX1077ETC-T

Manufacturer Part Number
MAX1077ETC-T
Description
Analog to Digital Converters - ADC
Manufacturer
Maxim Integrated
Datasheet

Specifications of MAX1077ETC-T

Number Of Channels
1
Architecture
SAR
Conversion Rate
1500 KSPs
Resolution
10 bit
Input Type
Differential
Snr
No
Interface Type
3-Wire (SPI, Microwire), QSPI
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
TQFN EP
Maximum Power Dissipation
1349 mW
Minimum Operating Temperature
- 40 C
Number Of Converters
1
Voltage Reference
Internal 2.048 V or External
partial power-down mode. Then repeat the same
sequence to enter full power-down mode (see Figure
7). Drive CNVST low, and allow at least 14 SCLK cycles
to elapse before driving CNVST high to exit full power-
down mode. While in full power-down mode, the refer-
ence is disabled to minimize power consumption. Be
sure to allow at least 2ms recovery time after exiting full
power-down mode for the reference to settle. In
1.5Msps, Single-Supply, Low-Power, True-
Differential, 10-Bit ADCs with Internal Reference
Figure 5. Interface-Timing Sequence
Figure 6. SPI Interface—Partial Power-Down Mode
Figure 7. SPI Interface—Full Power-Down Mode
10
______________________________________________________________________________________
MODE
CNVST
DOUT
SCLK
REF
CNVST
MODE
DOUT
CNVST
SCLK
DOUT
SCLK
REF
HIGH IMPEDANCE
t
SETUP
0
1ST SCLK RISING EDGE
0
1ST SCLK RISING EDGE
0
1
0
0
2
NORMAL
FIRST 8-BIT TRANSFER
0
ONE 8-BIT TRANSFER
NORMAL
D9
3
D9
4
D8
D9
D8
D8
D7
D7
1ST SCLK RISING EDGE
POWER-MODE SELECTION WINDOW
D7
D6
D6
ENABLED (2.048V)
D6
ENABLED (2.048V)
D5
8
D5
D5
DOUT GOES HIGH IMPEDANCE ONCE CNVST GOES HIGH
PPD
CNVST MUST GO HIGH AFTER THE 3RD BUT BEFORE THE 14TH SCLK RISING EDGE
partial/full power-down mode, maintain a logic low or a
logic high on SCLK to minimize power consumption.
Figure 8 shows the unipolar transfer function for the
MAX1077. Figure 9 shows the bipolar transfer function for
the MAX1079. The MAX1077 output is straight binary,
while the MAX1079 output is two’s complement.
D4
D3
0
D2
DOUT ENTERS TRI-STATE ONCE CNVST GOES HIGH
0
EXECUTE PARTIAL POWER-DOWN TWICE
D1
0
SECOND 8-BIT TRANSFER
D0
PPD
14
RECOVERY
0
S1
t
ACQUIRE
S0
0
16
CONTINUOUS-CONVERSION
SELECTION WINDOW
0
Transfer Function
0
0
DISABLED
FPD

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