MAX1077ETC-T Maxim Integrated, MAX1077ETC-T Datasheet - Page 15

• Manufacturer Part Number: MAX1077ETC-T
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1077ETC-T

• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 1500 KSPs
• Resolution: 10 bit
• Input Type: Differential
• Snr: No
• Interface Type: 3-Wire (SPI, Microwire), QSPI
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFN EP
• Maximum Power Dissipation: 1349 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: Internal 2.048 V or External

transmit-data register more than once. For single conver-
sions, idle CNVST high and pulse it low for the entire
conversion. The ADSP21_ _ _ STCTL and SRCTL regis-
ters should be configured for late framing (LAFR = 1)
and for an active-low frame (LTFS = 1, LRFS = 1) signal.
This is also the best way to enter the power-down modes
by setting the word length to 8 bits (SLEN = 1001).
Connect the V
when the MAX1077/MAX1079 are operating with a sup-
ply voltage higher than the DSP supply voltage (see
Figures 17 and 18).
For best performance, use PC boards. Wire-wrap
boards are not recommended. Board layout should
ensure that digital and analog signal lines are separat-
ed from each other. Do not run analog and digital
(especially clock) lines parallel to one another, or digital
lines underneath the ADC package.
Figure 20 shows the recommended system ground
connections. Establish a single-point analog ground
(star ground point) at GND, separate from the logic
ground. Connect all other analog grounds and DGND
to this star ground point for further noise reduction. The
ground return to the power supply for this ground
should be low impedance and as short as possible for
noise-free operation.
Figure 17. DSP Interface—Continuous Conversion
Figure 18. DSP Interface—Single-Conversion, Continuous/Burst Clock
Differential, 10-Bit ADCs with Internal Reference
CNVST
DOUT
SCLK
CNVST
DOUT
SCLK
Layout, Grounding, and Bypassing
S0
L
pin to the ADSP21_ _ _ supply voltage
1.5Msps, Single-Supply, Low-Power, True-
______________________________________________________________________________________
1
0
0
1
0
0
0
0
D9
0
D8
D9
D7
D8
D6
D5
D7
D4
D6
D3
High-frequency noise in the V
affect the ADC’s high-speed comparator. Bypass this
supply to the single-point analog ground with 0.01µF
and 10µF bypass capacitors. Minimize capacitor lead
lengths for best supply-noise rejection.
Integral nonlinearity (INL) is the deviation of the values on
an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. The static
linearity parameters for the MAX1077/MAX1079 are mea-
sured using the end-points method.
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A DNL
error specification of 1 LSB or less guarantees no missing
codes and a monotonic transfer function.
Aperture jitter (t
the time between the samples.
D5
D2
D4
D1
D3
D0
AJ
D2
S1
) is the sample-to-sample variation in
S0
D1
0
Differential Nonlinearity
D0
Integral Nonlinearity
S1
DD
power supply can
Aperture Jitter
S0
Definitions
1
0
0
1
0
0
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