NB7VPQ16MMNG ON Semiconductor, NB7VPQ16MMNG Datasheet - Page 10

• Manufacturer Part Number: NB7VPQ16MMNG
• Description: IC CML PRE-EMPH DRIVER 16QFN
• Manufacturer: ON Semiconductor

Specifications of NB7VPQ16MMNG

• Logic Type: CML Driver with Selectable Equalizer Receiver
• Supply Voltage: 1.71 V ~ 2.625 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Bits: -
• Lead Free Status / Rohs Status: Compliant

SDOUT/SCLKOUT
Serial Clock output pin. These pins are the outputs of the
5−bit SDI shift register and will produce the SDIN/SCLKIN
Cascaded Applications
NB7VPQ16Ms
Equalizer/Pre−Emphasis applications,
Figure 13.
cascaded chain of the Pre−Emphasis and equalizer shift
registers, (DUTA, DUTB and DUTC), 5−bits per register.
Upon the rising edge of the 5
valid data bit (D3) and 5
SDOUT is the Serial Data output pin; SCLKOUT is the
The NB7VPQ16M can be cascaded with multiple
Serial Data In, SDINA, is clocked with SCLKINA into the
D3
1
2
D2
5 Clocks
D1
3
in
D0
4
Figure 12. Simplified Cascaded Serial Data/Clock Timing Diagram
th
th
EQEN
clock will exit DUTA from
series
clock of SCLKINA, the first
5
SDIN
SCLKIN
for
as
DUTA
CASCADE APPLICATION
shown
various
http://onsemi.com
SCLKOUT
SDOUT
in
10
D3
5
signals after five serial clock cycles, see Figure 12. The
purpose of SDOUT and SCLKOUT is for use in cascade
applications, described below.
SDOUTA and SCLKOUTA and will be present at SDINB
and SCLKINB of DUTB and so on.
all devices are enabled and data is written into the
NB7VPQ16Ms with the contents of the PE shift registers.
When the data transfer is complete, SLOAD is brought
HIGH and all NB7VPQ16Ms are updated simultaneously.
After the PE control bits are clocked into their appropriate
registers, the Low−to−High transition of SLOAD will latch
the data bits for the Pre−Emphasis DACs.
When SLOAD is brought LOW, the PE shift registers of
D2
6
D1
7
D0
8
EQEN
9
SDIN
SCLKIN
DUTB
SCLKOUT
SDOUT