MAX1303BEUP-T Maxim Integrated, MAX1303BEUP-T Datasheet - Page 19

• Manufacturer Part Number: MAX1303BEUP-T
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1303BEUP-T

• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 115 KSPs
• Resolution: 16 bit
• Input Type: Single-Ended/Differential
• Snr: 90 dB
• Interface Type: Microwire, QSPI, Serial, SPI
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-24
• Maximum Power Dissipation: 879 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: Internal, External

The MAX1303 differential common-mode range
(V
valid conversion results. The differential common-mode
range is defined as:
In addition to the common-mode input voltage limita-
tions, each individual analog input must be limited to
±6V with respect to AGND1.
The range-select bits R[2:0] in the analog input config-
uration bytes determine the full-scale range for the cor-
responding channel (Tables 2 and 6). Figures 8, 9, and
10 show the valid analog input voltage ranges for the
MAX1303 when operating with FSR = V
V
area contains the valid common-mode voltage ranges
that support the entire FSR.
The MAX1303 features a serial interface that is compat-
ible with SPI/QSPI and MICROWIRE devices. DIN,
DOUT, SCLK, CS, and SSTRB facilitate bidirectional
communication between the MAX1303 and the master
at SCLK rates up to 10MHz (internal clock mode, mode
2), 3.67MHz (external clock mode, mode 0), or
4.39MHz (external acquisition mode, mode 1). The
master, typically a microcontroller, should use the
CPOL = 0, CPHA = 0, SPI transfer format, as shown in
the timing diagrams of Figures 1, 2, and 3.
The digital interface is used to:
• Select single-ended or true-differential input channel
• Select the unipolar or bipolar input range
• Select the mode of operation:
• Initiate conversions and read results
CS enables communication with the MAX1303. When CS is
low, data is clocked into the device from DIN on the rising edge
of SCLK and data is clocked out of DOUT on the falling edge
of SCLK. When CS is high, activity on SCLK and DIN is ignored
and DOUT is high impedance allowing DOUT to be shared
with other peripherals. SSTRB is never high impedance
and therefore cannot be shared with other peripherals.
REF
CMDR
configurations
, and FSR = 2 x V
External clock (mode 0)
External acquisition (mode 1)
Internal clock (mode 2)
Reset (mode 4)
Partial power-down (mode 6)
Full power-down (mode 7)
) must remain within -4.75V to +5.5V to obtain
Differential Common-Mode Range
V
CMDR
______________________________________________________________________________________
=
(
REF
CH
_
, respectively. The shaded
4-Channel, ±V
+
)
+
2
Digital Interface
(
CH
Chip Select (CS)
_
−
)
REF
/2, FSR =
Figure 8. Common-Mode Voltage vs. Input Voltage (FSR = V
Figure 9. Common-Mode Voltage vs. Input Voltage (FSR = 2 x
V
Figure 10. Common-Mode Voltage vs. Input Voltage (FSR = 4 x
V
REF
REF
REF
)
)
Multirange Inputs,
-2
-4
-6
-2
-4
-6
-2
-4
-6
6
4
2
0
6
4
2
0
6
4
2
0
Serial 16-Bit ADC
-8
-8
-8
-6
-6
-6
-4
-4
-4
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
-2
-2
-2
0
0
0
2
2
2
V
V
V
REF
REF
REF
4
4
4
= 4.096V
= 4.096V
= 4.096V
6
6
6
8
8
8
REF
19
)