MAX1303BEUP-T Maxim Integrated, MAX1303BEUP-T Datasheet - Page 22

• Manufacturer Part Number: MAX1303BEUP-T
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1303BEUP-T

• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 115 KSPs
• Resolution: 16 bit
• Input Type: Single-Ended/Differential
• Snr: 90 dB
• Interface Type: Microwire, QSPI, Serial, SPI
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-24
• Maximum Power Dissipation: 879 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: Internal, External

The MAX1303 contains one byte-wide mode-control
register. The timing diagram of Figure 14 shows how to
use the mode-control byte, and the mode-control byte
format is shown in Table 7. The mode-control byte is
used to select the conversion method and to control the
power modes of the MAX1303.
The conversion method is selected using the mode-con-
trol byte (see the Mode Control section), and the conver-
sion is initiated using a conversion start command (Table
3, and Figures 1, 2, and 3).The MAX1303 converts ana-
log signals to digital data using one of three methods:
•
4-Channel, ±V
Serial 16-Bit ADC
Figure 13. Ideal Unipolar Transfer Function, Single-Ended
Input, 0 to +FSR
Table 7. Mode-Control Byte
22
BIT NUMBER
External Clock Mode, Mode 0 (Figure 1)
• Highest maximum throughput (see the Electrical
• User controls the sample instant
______________________________________________________________________________________
7
6
5
4
3
2
1
0
Characteristics table)
FFFD
FFFF
FFFE
8001
8000
7FFF
0003
0002
0001
0000
(AGND1)
0
1
BIT NAME
2
START
Selecting the Conversion Method
3
M2
M1
M0
1
0
0
0
INPUT VOLTAGE (LSB [DECIMAL])
32,768
FSR
Start Bit. The first logic 1 after CS goes low defines the beginning of the mode-control byte.
Mode-Control Bits. M[2:0] select the mode of operation as shown in Table 8.
Bit 3 must be a logic 1 for the mode-control byte.
Bit 2 must be a logic 0 for the mode-control byte.
Bit 1 must be a logic 0 for the mode-control byte.
Bit 0 must be a logic 0 for the mode-control byte.
1 LSB =
REF
65,536 x 4.096V
FSR x V
Mode Control
65,533 65,535
REF
Multirange Inputs,
•
•
The MAX1303’s fastest maximum throughput rate is
achieved operating in external clock mode. SCLK con-
trols both the acquisition and conversion of the analog
signal, facilitating precise control over when the analog
signal is captured. The analog input sampling instant is
at the falling edge of the 14th SCLK (Figure 1).
Since SCLK drives the conversion in external clock
mode, the SCLK frequency should remain constant
while the conversion is clocked. The minimum SCLK
frequency prevents droop in the internal sampling
capacitor voltages during conversion.
SSTRB remains low in the external clock mode, and as a
result may be left unconnected if the MAX1303 will
always be used in the external clock mode.
• CS remains low during the conversion
• User supplies SCLK throughout the ADC con-
External Acquisition Mode, Mode 1 (Figure 2)
• Lowest maximum throughput (see the Electrical
• User controls the sample instant
• User supplies two bytes of SCLK, then drives
• After SSTRB transitions high, the user supplies
Internal Clock Mode, Mode 2 (Figure 3)
• High maximum throughput (see the Electrical
• The internal clock controls the sampling instant
• User supplies one byte of SCLK, then drives CS
• After SSTRB transitions high, the user supplies
DESCRIPTION
version and reads data at DOUT
Characteristics table)
CS high to relieve processor load while the
ADC converts
two bytes of SCLK and reads data at DOUT
Characteristics table)
high to relieve processor load while the ADC
converts
two bytes of SCLK and reads data at DOUT
External Clock Mode (Mode 0)