S9S12G240F0CLFR Freescale Semiconductor, S9S12G240F0CLFR Datasheet - Page 215
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S9S12G240F0CLFR
Manufacturer Part Number
S9S12G240F0CLFR
Description
16-bit Microcontrollers - MCU 16BIT 240KB FLASH
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G240F0CLFR
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
240 KB
Data Ram Size
4 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-48
Mounting Style
SMD/SMT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S9S12G240F0CLFR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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1
2.4.3.18
Freescale Semiconductor
Read: Anytime
Write: Anytime
Address 0x0244 (G1, G2)
Address 0x0244 (G3)
PERT
PERT
PERT
Field
Reset
Reset
7-2
1
0
W
W
R
R
Port T pull device enable—Enable pull device on input pin
This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has
no effect. The polarity is selected by the related polarity select register bit.
1 Pull device enabled
0 Pull device disabled
Port T pull device enable—Enable pull device on input pin
This bit controls whether a pull device on the associated port input pin is active. The polarity is selected by the related
polarity select register bit. If this pin is used as IRQ only a pullup device can be enabled.
1 Pull device enabled
0 Pull device disabled
Port T pull device enable—Enable pull device on input pin
This bit controls whether a pull device on the associated port input pin is active. The polarity is selected by the related
polarity select register bit. If this pin is used as XIRQ only a pullup device can be enabled.
1 Pull device enabled
0 Pull device disabled
PERT7
Port T Pull Device Enable Register (PERT)
0
0
0
7
7
PERT6
Figure 2-19. Port T Pull Device Enable Register (PERT)
0
0
0
6
6
Table 2-38. PERT Register Field Descriptions
MC9S12G Family Reference Manual, Rev.1.23
PERT5
PERT5
0
0
5
5
PERT4
PERT4
0
0
4
4
Description
PERT3
PERT3
0
0
3
3
PERT2
PERT2
2
0
2
0
Port Integration Module (S12GPIMV1)
PERT1
PERT1
Access: User read/write
Access: User read/write
0
0
1
1
PERT0
PERT0
0
0
0
0
217
1
1
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