S9S12G240F0CLFR Freescale Semiconductor, S9S12G240F0CLFR Datasheet - Page 746
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S9S12G240F0CLFR
Manufacturer Part Number
S9S12G240F0CLFR
Description
16-bit Microcontrollers - MCU 16BIT 240KB FLASH
Manufacturer
Freescale Semiconductor
Datasheet
1.S9S12G96F0CLL.pdf
(1292 pages)
Specifications of S9S12G240F0CLFR
Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
240 KB
Data Ram Size
4 KB
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-48
Mounting Style
SMD/SMT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S9S12G240F0CLFR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Timer Module (TIM16B6CV3)
22.4.1
The prescaler divides the bus clock by 1, 2, 4, 8, 16, 32, 64 or 128. The prescaler select bits, PR[2:0], select
the prescaler divisor. PR[2:0] are in timer system control register 2 (TSCR2).
The prescaler divides the bus clock by a prescalar value. Prescaler select bits PR[2:0] of in timer system
control register 2 (TSCR2) are set to define a prescalar value that generates a divide by 1, 2, 4, 8, 16, 32,
64 and 128 when the PRNT bit in TSCR1 is disabled.
748
PTPSR[7:0]
PRE-PRESCALER
PR[2:1:0]
Prescaler
PRESCALER
16-BIT COMPARATOR
16-BIT COMPARATOR
16-BIT COMPARATOR
EDG0A
EDG1A
TCNT(hi):TCNT(lo)
16-BIT COUNTER
CHANNELn-1
CHANNEL2
CHANNEL 1
CHANNEL 0
TCn-1
TC0
TC1
EDG7A
EDG7B
EDG0B
EDG1B
1
MUX
0
Figure 22-22. Detailed Timer Block Diagram
PACLK/65536
MC9S12G Family Reference Manual,
PACLK/256
PACLK
DETECT
DETECT
TE
DETECT
EDGE
EDGE
EDGE
Cn-1F
C0F
C1F
MUX
OM:OL1
OM:OL0
OM:OL7
TOV1
TOV0
TOV7
CLK[1:0]
TOF
TOI
IOC0
CxF
CxI
C0F
C1F
IOC1
Cn-1F
IOCn-1
INTERRUPT
Rev.1.23
LOGIC
n is channels number.
IOC0 PIN
IOCn-1 PIN
IOC1 PIN
LOGIC
LOGIC
LOGIC
CH. 1 COMPARE
CH. 0 CAPTURE
CH. 1 CAPTURE
CH. 0COMPARE
CH. n-1COMPARE
CH.n-1 CAPTURE
PA INPUT
Freescale Semiconductor
IOCn-1 PIN
IOC0 PIN
IOC1 PIN
TOF
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