C8051F961-A-GM Silicon Labs, C8051F961-A-GM Datasheet - Page 438
C8051F961-A-GM
Manufacturer Part Number
C8051F961-A-GM
Description
8-bit Microcontrollers - MCU 128KB, DC-DC, LCD AES, QFN40
Manufacturer
Silicon Labs
Datasheet
1.C8051F960-A-GQ.pdf
(492 pages)
Specifications of C8051F961-A-GM
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
128 KB
Data Ram Size
8448 B
On-chip Adc
Yes
Operating Supply Voltage
2.5 V to 3.3 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
QFN-40
Mounting Style
SMD/SMT
Number Of Programmable I/os
34
Number Of Timers
4
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C8051F96x
SFR Definition 31.1. SPI1CFG: SPI1 Configuration
SFR Page = 0x2; SFR Address = 0xA1
438
Note: In slave mode, data on MOSI is sampled in the center of each data bit. In master mode, data on MISO is
Name
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
sampled one SYSCLK before the end of each data bit, to provide maximum settling time for the slave device.
See Table 31.1 for timing parameters.
SLVSEL
SPIBSY
MSTEN
RXBMT
CKPHA
CKPOL
SPIBSY
NSSIN
SRMT
Name
R
7
0
MSTEN
SPI Busy.
This bit is set to logic 1 when a SPI transfer is in progress (master or slave mode).
Master Mode Enable.
0: Disable master mode. Operate in slave mode.
1: Enable master mode. Operate as a master.
SPI1 Clock Phase.
0: Data centered on first edge of SCK period.
1: Data centered on second edge of SCK period.
SPI1 Clock Polarity.
0: SCK line low in idle state.
1: SCK line high in idle state.
Slave Selected Flag.
This bit is set to logic 1 whenever the NSS pin is low indicating SPI1 is the selected
slave. It is cleared to logic 0 when NSS is high (slave not selected). This bit does
not indicate the instantaneous value at the NSS pin, but rather a de-glitched ver-
sion of the pin input.
NSS Instantaneous Pin Input.
This bit mimics the instantaneous value that is present on the NSS port pin at the
time that the register is read. This input is not de-glitched.
Shift Register Empty (valid in slave mode only).
This bit will be set to logic 1 when all data has been transferred in/out of the shift
register, and there is no new information available to read from the transmit buffer
or write to the receive buffer. It returns to logic 0 when a data byte is transferred to
the shift register from the transmit buffer or by a transition on SCK. SRMT = 1 when
in Master Mode.
Receive Buffer Empty (valid in slave mode only).
This bit will be set to logic 1 when the receive buffer has been read and contains no
new information. If there is new information available in the receive buffer that has
not been read, this bit will return to logic 0. RXBMT = 1 when in Master Mode.
R/W
6
0
CKPHA
R/W
5
0
CKPOL
R/W
Rev. 0.5
4
0
SLVSEL
Function
R
3
0
*
NSSIN
*
R
2
1
SRMT
R
1
1
RXBMT
R
0
1
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